H10P 90/1918
Including charge trapping layers
Official title: {including charge trapping layers, e.g. polycrystalline materials}
H10P90/1918 (Including charge trapping layers) appears on 87 US grants and 104 published applications in this corpus.
Search patents in H10P- Granted patents
- 87
- Published applications
- 104
- Assignees
- 29
- Inventors
- 164
- Latest grant
- 2 Jun 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1991 | 1 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 0 | 0 |
| 1998 | 1 | 0 |
| 1999 | 0 | 0 |
| 2000 | 0 | 0 |
| 2001 | 0 | 0 |
| 2002 | 0 | 0 |
| 2003 | 0 | 0 |
| 2004 | 0 | 0 |
| 2005 | 0 | 0 |
| 2006 | 0 | 0 |
| 2007 | 0 | 1 |
| 2008 | 0 | 0 |
| 2009 | 0 | 0 |
| 2010 | 0 | 2 |
| 2011 | 0 | 3 |
| 2012 | 0 | 0 |
| 2013 | 5 | 2 |
| 2014 | 3 | 5 |
| 2015 | 1 | 1 |
| 2016 | 1 | 3 |
| 2017 | 4 | 8 |
| 2018 | 7 | 12 |
| 2019 | 10 | 4 |
| 2020 | 6 | 12 |
| 2021 | 11 | 7 |
| 2022 | 9 | 16 |
| 2023 | 7 | 9 |
| 2024 | 9 | 9 |
| 2025 | 6 | 5 |
| 2026 | 6 | 5 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Trapping layer for a radio frequency die and methods of formation2 Jun 2026US 12,648,226 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Support for a semiconductor structure5 May 2026US 12,622,236 B2Soitec
- Device with airgap structure14 Apr 2026US 12,604,735 B2GLOBALFOUNDRIES U. S. Inc.
- Integrated structure with trap rich regions and low resistivity regions24 Mar 2026US 12,588,282 B2GLOBALFOUNDRIES U. S. Inc.
- Method for forming a high resistivity handle support for composite substrate17 Mar 2026US 12,581,922 B2Soitec
- Method for manufacturing a structure comprising a barrier layer to prevent diffusion of atomic species27 Aug 2026US 2026/0255879 A1
- Carrier comprising a charge-trapping layer, composite substrate comprising such a carrier and associated production methods13 Aug 2026US 2026/0239940 A1
- Systems and methods for porous backside contacts16 Jul 2026US 2026/0206313 A1IQE plc
- Manufacture method for manufacturing a wafer structure25 Jun 2026US 2026/0182428 A1Okmetic Ltd.
- Methods of processing semiconductor-on-insulator structures using clean-and-etch operation15 Jan 2026US 2026/0018457 A1GlobalWafers Co., Ltd.
Most cited
By later US patents
- SOI substrate having a high heavy metal gettering effect for semiconductor device86US 5,773,152 ANEC Corporation · 1998
- Managed substrate effects for stabilized SOI FETs16US 10,546,747 B2pSemi Corporation · 2020
- Substrate having semiconductor-on-insulator structure with gettering sites and production method thereof15US 5,063,113 AFujitsu Limited · 1991
- Managed substrate effects for stabilized SOI FETs13US 10,276,371 B2pSemi Corporation · 2019
- Handle wafer for high resistivity trap-rich SOI8US 9,269,591 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2016