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US 12,588,282 B2Granted
Integrated structure with trap rich regions and low resistivity regions
AssigneeGlobalFoundries U.S. Inc.
InventorsVibhor Jain, Crystal R. Kenney, John J. Pekarik
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Abstract
The present disclosure relates to semiconductor structures and, more particularly, to a substrate with trap rich and low resistivity regions and methods of manufacture. The structure includes: a high resistivity semiconductor substrate; an active device over the high resistivity semiconductor substrate; and a low resistivity region floating in the high resistivity semiconductor substrate and which is below the active device.
Claims15
A structure comprising:
- a high resistivity semiconductor substrate;
- an active device over the high resistivity semiconductor substrate;
- and
- a low resistivity region floating in the high resistivity semiconductor substrate and which is below the active device, wherein
- the high resistivity semiconductor substrate comprises a high resistivity handle substrate underneath a buried insulator layer and a top semiconductor layer, wherein the low resistivity region comprises boron, and
- the low resistivity region is floating below and not touching the buried insulator layer and the active device in the high resistivity handle substrate, with a high resistivity region between the active device and the low resistivity region.
3 more elements
A structure comprising:
- a handle substrate comprising high resistivity semiconductor material;
- a buried insulator layer above the handle substrate;
- a semiconductor layer on the buried insulator layer;
- an active device over the semiconductor layer;
- a non-single-crystal semiconductor region in the handle substrate underneath the active device and contacting an underside of the buried insulator layer;
- and
- a low resistivity region comprises boron floating in the handle substrate and which is below the active device.
4 more elements
A structure comprising:
- a handle substrate comprising high resistivity semiconductor material;
- a buried insulator layer above the handle substrate;
- a semiconductor layer on the buried insulator layer;
- an active device over the semiconductor layer;
- a non-single-crystal semiconductor region in the handle substrate underneath the active device and contacting an underside of the buried insulator layer;
- a low resistivity region floating in the handle substrate and which is below the active device;
- a second device over the semiconductor layer, wherein the high resistivity semiconductor material under the second device is devoid of the low resistivity region and the non-single-crystal semiconductor region;
- a third device over the semiconductor layer, wherein the high resistivity semiconductor material under the third device is devoid of the low resistivity region and includes the non-single-crystal semiconductor region;
- and
- a fourth device over the handle substrate, wherein the high resistivity semiconductor material under the fourth device is devoid of the non-single-crystal semiconductor region and includes the low resistivity region.
7 more elements
Dependencies are inferred from the claim text.