Trapping layer for a radio frequency die and methods of formation

A method, comprising:

• forming a logic die;
• forming, after forming the logic die, a radio frequency (RF) die comprising;
• etching a top surface of a high-resistance substrate;
• forming a polysilicon seed layer on the top surface of the high-resistance substrate after etching the top surface of the high-resistance substrate;
• and
• forming a trapping layer on the polysilicon seed layer, wherein a grain size of the polysilicon seed layer is less than a grain size of the trapping layer;
• reducing a thickness of the high-resistance substrate of the RF die;
• and
• bonding, after reducing the thickness of the high-resistance substrate of the RF die, the logic die and the RF die to form an RF device die,
• wherein a high-resistance substrate of the logic die and the high-resistance substrate of the RF die are on opposite sides of the RF device die,
• wherein a thickness of the high-resistance substrate of the logic die is greater than the thickness of high-resistance substrate of the RF die, and
• wherein the logic die and the RF die are vertically stacked in the RF device die.

A radio frequency (RF) device die, comprising:

• a logic die comprising a high-resistance substrate of the logic die;
• and
• an RF die, bonded with the logic die, comprising:
• a high-resistance substrate of the RF die, wherein a thickness of the high-resistance substrate of the logic die is greater than the thickness of the high-resistance substrate of the RF die,
• a polysilicon trapping layer on a top surface of the high-resistance substrate of the RF die, wherein the polysilicon trapping layer is doped with one or more types of dopants and comprises a first region and a second region that is side by side with the first region, wherein the first region includes a first combination of the one or more types of dopants and the second region includes a second combination of the one or more types of dopants, wherein the second combination is different from the first combination,
• an insulator layer on the polysilicon trapping layer, and
• an RF device layer having a first side directly on the insulator layer and a second side, opposite of the first side, bonded to the logic die, wherein a high-resistance substrate of the logic die and the high-resistance substrate of the RF die are on opposite sides of the RF device die.