Handle wafer for high resistivity trap-rich SOI

A silicon-on-insulator (SOI) substrate, comprising:

• a high resistivity silicon handle wafer having a scratched top surface with depressions extending in lines across the scratched top surface of the high resistivity silicon handle wafer;
• a trap-rich layer, comprising a re-crystallized amorphous silicon material, which is disposed within the handle wafer at a position extending from the scratched top surface of the handle wafer to an underlying crystalline layer within the handle wafer, wherein the trap rich layer comprises dislocations or oxidation induced stacking faults configured to trap carriers;
• a thermal oxide layer having a first side abutting the scratched top surface of the handle wafer at an interface with the trap-rich layer;
• and
• a thin layer of active silicon abutting a second side of the thermal oxide layer that opposes the first side.

A silicon-on-insulator (SOI) substrate, comprising:

• a high-resistivity silicon handle substrate;
• a trap-rich layer comprising re-crystallized amorphous silicon having oxidation induced stacking faults extending from a top surface of the high-resistivity silicon handle substrate to an underlying crystalline layer within the high-resistivity silicon handle substrate;
• an oxide layer having a first side abutting the top surface of the high-resistivity silicon handle substrate at an interface with the trap-rich layer, wherein the top surface of the high-resistivity silicon handle substrate is a scratched top surface with depressions extending in lines across the top surface of the substrate and forming protrusions extending into the oxide layer;
• and
• a thin layer of active silicon abutting a second side of the oxide layer that opposes the first side.