H10P 76/408
Characterised by their sizes, orientations, dispositions, behaviours or shapes
Official title: {characterised by their sizes, orientations, dispositions, behaviours or shapes}
H10P76/408 (Characterised by their sizes, orientations, dispositions, behaviours or shapes) appears on 5,048 US grants and 5,464 published applications in this corpus.
Search patents in H10P- Granted patents
- 5,048
- Published applications
- 5,464
- Assignees
- 569
- Inventors
- 7,390
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 0 | 0 |
| 1978 | 1 | 0 |
| 1979 | 0 | 0 |
| 1980 | 5 | 0 |
| 1981 | 6 | 0 |
| 1982 | 11 | 0 |
| 1983 | 14 | 0 |
| 1984 | 9 | 0 |
| 1985 | 10 | 0 |
| 1986 | 13 | 0 |
| 1987 | 16 | 0 |
| 1988 | 19 | 0 |
| 1989 | 16 | 0 |
| 1990 | 7 | 0 |
| 1991 | 5 | 0 |
| 1992 | 4 | 0 |
| 1993 | 13 | 0 |
| 1994 | 18 | 0 |
| 1995 | 15 | 0 |
| 1996 | 9 | 0 |
| 1997 | 17 | 0 |
| 1998 | 34 | 0 |
| 1999 | 39 | 0 |
| 2000 | 32 | 0 |
| 2001 | 39 | 8 |
| 2002 | 30 | 30 |
| 2003 | 43 | 47 |
| 2004 | 45 | 65 |
| 2005 | 47 | 73 |
| 2006 | 58 | 85 |
| 2007 | 52 | 137 |
| 2008 | 63 | 173 |
| 2009 | 91 | 221 |
| 2010 | 133 | 183 |
| 2011 | 169 | 151 |
| 2012 | 180 | 198 |
| 2013 | 177 | 172 |
| 2014 | 232 | 275 |
| 2015 | 267 | 316 |
| 2016 | 314 | 318 |
| 2017 | 307 | 278 |
| 2018 | 284 | 302 |
| 2019 | 351 | 396 |
| 2020 | 411 | 457 |
| 2021 | 308 | 363 |
| 2022 | 279 | 311 |
| 2023 | 233 | 271 |
| 2024 | 245 | 264 |
| 2025 | 242 | 229 |
| 2026 | 134 | 141 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Assembly structure including a plurality of spacers and method of manufacturing the same6 Oct 2026US 12,757,375 B2Nanya Technology Corporation
- Semiconductor device, semiconductor structure and method for fabricating semiconductor device and semiconductor structure using tilted etch process6 Oct 2026US 12,757,661 B2Nanya Technology Corporation
- Method of manufacturing memory device using self-aligned double patterning (SADP)6 Oct 2026US 12,757,690 B2Nanya Technology Corporation
- Method for fabricating semiconductor device29 Sep 2026US 12,751,222 B2Samsung Electronics Co., Ltd.
- Substrate processing method and apparatus22 Sep 2026US 12,745,611 B2ASM IP Holding B. V.
- Selective etch of a stack with a carbon containing mask8 Oct 2026US 2026/0314342 A1Lam Research Corporation
- Lithography method using photo mask8 Oct 2026US 2026/0314343 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Structure and Method for Deep Trench Capacitor with Reduced Deformation1 Oct 2026US 2026/0304797 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Redistribution layer metallic layout structure and method with warpage reduction1 Oct 2026US 2026/0305234 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Method of forming pattern and method of manufacturing semiconductor device1 Oct 2026US 2026/0305268 A1Samsung Electronics Co., Ltd.
Most cited
By later US patents
- Method of spacer patterning to form a target integrated circuit pattern3,272US 9,576,814 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2017
- Method for reducing, by a factor or 2.sup.-N, the minimum masking pitch of a photolithographic process1,059US 5,328,810 AMicron Technology, Inc. · 1994
- Method for integrated circuit patterning805US 9,184,054 B1Taiwan Semiconductor Manufacturing Company.Ltd · 2015
- Frequency doubling using spacer mask774US 7,807,578 B2APPLIED Materials.Inc. · 2010
- Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures742US 7,611,980 B2Micron Technology, Inc. · 2009