Method of spacer patterning to form a target integrated circuit pattern

A method comprising:

• providing a patterned first material over a substrate, the substrate including a plurality of hard mask layers;
• depositing a second material to a second thickness over the substrate, over the patterned first material, and onto sidewalls of the patterned first material;
• depositing a third material over the second material;
• and
• patterning the second and third materials to form trenches, wherein the second material remains deposited over the patterned first material and on the sidewalls of the patterned first material.

A method of forming a target pattern for an integrated circuit, the method comprising:

• decomposing the target pattern to at least a first mask, the first mask having a first mask pattern, and a second mask, the second mask having a second mask pattern, wherein at least a portion of the first mask pattern overlaps with at least a portion of the second mask pattern;
• providing a patterned first spacer layer over a substrate;
• forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto the sidewalls of the patterned first spacer layer;
• forming a first material layer over the second spacer layer;
• and
• patterning the first material layer with the second mask wherein the second spacer layer and the patterned first material layer collectively define a second plurality of features.