H10P 76/4085
Characterised by the processes involved to create the masks
Official title: {characterised by the processes involved to create the masks}
H10P76/4085 (Characterised by the processes involved to create the masks) appears on 4,548 US grants and 4,991 published applications in this corpus.
Search patents in H10P- Granted patents
- 4,548
- Published applications
- 4,991
- Assignees
- 516
- Inventors
- 6,652
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1980 | 4 | 0 |
| 1981 | 3 | 0 |
| 1982 | 9 | 0 |
| 1983 | 11 | 0 |
| 1984 | 9 | 0 |
| 1985 | 8 | 0 |
| 1986 | 10 | 0 |
| 1987 | 11 | 0 |
| 1988 | 17 | 0 |
| 1989 | 15 | 0 |
| 1990 | 6 | 0 |
| 1991 | 5 | 0 |
| 1992 | 4 | 0 |
| 1993 | 13 | 0 |
| 1994 | 15 | 0 |
| 1995 | 11 | 0 |
| 1996 | 8 | 0 |
| 1997 | 13 | 0 |
| 1998 | 17 | 0 |
| 1999 | 22 | 0 |
| 2000 | 16 | 0 |
| 2001 | 24 | 8 |
| 2002 | 24 | 20 |
| 2003 | 34 | 36 |
| 2004 | 34 | 54 |
| 2005 | 33 | 56 |
| 2006 | 48 | 74 |
| 2007 | 42 | 106 |
| 2008 | 53 | 150 |
| 2009 | 75 | 198 |
| 2010 | 117 | 164 |
| 2011 | 145 | 131 |
| 2012 | 162 | 186 |
| 2013 | 165 | 158 |
| 2014 | 214 | 250 |
| 2015 | 244 | 289 |
| 2016 | 278 | 288 |
| 2017 | 293 | 258 |
| 2018 | 266 | 278 |
| 2019 | 321 | 379 |
| 2020 | 393 | 434 |
| 2021 | 291 | 340 |
| 2022 | 260 | 288 |
| 2023 | 220 | 256 |
| 2024 | 235 | 248 |
| 2025 | 223 | 213 |
| 2026 | 127 | 129 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Assembly structure including a plurality of spacers and method of manufacturing the same6 Oct 2026US 12,757,375 B2Nanya Technology Corporation
- Semiconductor device, semiconductor structure and method for fabricating semiconductor device and semiconductor structure using tilted etch process6 Oct 2026US 12,757,661 B2Nanya Technology Corporation
- Method of manufacturing memory device using self-aligned double patterning (SADP)6 Oct 2026US 12,757,690 B2Nanya Technology Corporation
- Method for fabricating semiconductor device29 Sep 2026US 12,751,222 B2Samsung Electronics Co., Ltd.
- Substrate processing method and apparatus22 Sep 2026US 12,745,611 B2ASM IP Holding B. V.
- Selective etch of a stack with a carbon containing mask8 Oct 2026US 2026/0314342 A1Lam Research Corporation
- Redistribution layer metallic layout structure and method with warpage reduction1 Oct 2026US 2026/0305234 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Patterning method applicable in semiconductor processing1 Oct 2026US 2026/0305270 A1
- Substrate treatment apparatus and substrate treatment method17 Sep 2026US 2026/0277107 A1Tokyo Electron Limited
- Assembly structure including a plurality of spacers and method of manufacturing the same17 Sep 2026US 2026/0282318 A1Nanya Technology Corporation
Most cited
By later US patents
- Method of spacer patterning to form a target integrated circuit pattern3,272US 9,576,814 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2017
- Method for reducing, by a factor or 2.sup.-N, the minimum masking pitch of a photolithographic process1,059US 5,328,810 AMicron Technology, Inc. · 1994
- Method for integrated circuit patterning805US 9,184,054 B1Taiwan Semiconductor Manufacturing Company.Ltd · 2015
- Frequency doubling using spacer mask774US 7,807,578 B2APPLIED Materials.Inc. · 2010
- Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures742US 7,611,980 B2Micron Technology, Inc. · 2009