A semi-product of a semiconductor device, comprising:
- a first isolation structure, a second isolation structure, and a third isolation structure disposed in a semiconductor substrate;
- a transistor, disposed between the first isolation structure and the second isolation structure, comprising a gate electrode and a first source/drain (S/D) region;
- a resistor, disposed between the second isolation structure and the third isolation structure, comprising a resistor electrode;
- an interlayer dielectric (ILD) layer, disposed over the semiconductor substrate;
- a first hard mask layer disposed on and in contact with the ILD layer, wherein the first hard mask layer has a first opening, a second opening, a third opening, and a fourth opening formed therethrough;
- and
- a second hard mask layer disposed on and in contact with the first hard mask layer, wherein the second hard mask layer has a fifth opening and a sixth opening formed therethrough,
- wherein the first opening and the second opening are respectively connected the fifth opening along two sidewalls of the fifth opening, and extend from the fifth opening to the ILD layer, wherein the first opening and the second opening are aligned with the transistor from a top view perspective;
- wherein the third opening and the fourth opening are respectively connected to the sixth opening along two sidewalls of the sixth opening, and extend from the sixth opening to the ILD layer, wherein the third opening and the fourth opening are aligned with the resistor electrode from the top view perspective;
- wherein the first S/D region is disposed between the gate electrode and the second isolation structure, and is electrically connected to the resistor electrode;
- wherein widths of the first opening, the second opening, the third opening, and the fourth opening are equal, wherein a width of each of the fifth opening and the sixth opening is larger than a width of each of the first opening, the second opening, the third opening, and the fourth opening.