H10D 84/8316
The igfets characterised by having gate sidewall spacers specially adapted for integration
Official title: {the IGFETs characterised by having gate sidewall spacers specially adapted for integration}
H10D84/8316 (The igfets characterised by having gate sidewall spacers specially adapted for integration) appears on 550 US grants and 673 published applications in this corpus.
Search patents in H10D- Granted patents
- 550
- Published applications
- 673
- Assignees
- 66
- Inventors
- 1,091
- Latest grant
- 29 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1991 | 1 | 0 |
| 1992 | 1 | 0 |
| 1993 | 1 | 0 |
| 1994 | 1 | 0 |
| 1995 | 2 | 0 |
| 1996 | 1 | 0 |
| 1997 | 2 | 0 |
| 1998 | 5 | 0 |
| 1999 | 4 | 0 |
| 2000 | 5 | 0 |
| 2001 | 3 | 0 |
| 2002 | 0 | 0 |
| 2003 | 0 | 0 |
| 2004 | 0 | 2 |
| 2005 | 0 | 0 |
| 2006 | 2 | 1 |
| 2007 | 1 | 6 |
| 2008 | 0 | 9 |
| 2009 | 3 | 2 |
| 2010 | 5 | 3 |
| 2011 | 3 | 3 |
| 2012 | 5 | 4 |
| 2013 | 9 | 6 |
| 2014 | 4 | 15 |
| 2015 | 21 | 22 |
| 2016 | 23 | 29 |
| 2017 | 30 | 29 |
| 2018 | 45 | 49 |
| 2019 | 52 | 57 |
| 2020 | 61 | 70 |
| 2021 | 48 | 58 |
| 2022 | 44 | 55 |
| 2023 | 41 | 67 |
| 2024 | 50 | 69 |
| 2025 | 50 | 71 |
| 2026 | 27 | 46 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Method for forming a semiconductor device by recessing semiconductor layers and inner spacers29 Sep 2026US 12,751,079 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Field effect transistor with inner spacer liner layer and method25 Aug 2026US 12,720,838 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor device with supporting structures and method for forming the same25 Aug 2026US 12,720,846 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor device having insulating layers with multiple material properties and method of fabricating same25 Aug 2026US 12,721,151 B2Samsung Electronics Co., Ltd.
- Heat removing layer surrounding a transistor11 Aug 2026US 12,707,968 B2Invention and Collaboration Laboratory, Inc.
- Nanosheet semiconductor device and method for manufacturing the same1 Oct 2026US 2026/0304925 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Lateral electrical path from contact to contact24 Sep 2026US 2026/0293273 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Vertical metal liners for gate merge in sequential fets17 Sep 2026US 2026/0282529 A1International Business Machines Corporation
- Interconnect inner spacer configurations23 Jul 2026US 2026/0214957 A1International Business Machines Corporation
- Semiconductor structure and method for forming the same9 Jul 2026US 2026/0198067 A1Taiwan Semiconductor Manufacturing Company.Ltd
Most cited
By later US patents
- CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation144US 5,757,045 ATaiwan Semiconductor Manufacturing Company.Ltd · 1998
- Methods of forming gate structures by a gate-cut-last process and the resulting structures85US 9,064,932 B1Globalfoundries Inc. · 2015
- CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation process83US 5,668,024 ATaiwan Semiconductor Manufacturing Company.Ltd · 1997
- Air gap spacer between contact and gate region75US 9,716,158 B1International Business Machines Corporation · 2017
- Method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths64US 5,963,803 AAdvanced Micro Devices, Inc. · 1999