Nanosheet semiconductor device and method for manufacturing the same

A method for manufacturing a semiconductor device, comprising:

• forming a base semiconductor structure over a substrate that includes a protrusion;
• forming a recess that recesses the protrusion of the substrate and that penetrates the base semiconductor structure so that the base semiconductor structure is formed with a first stack portion and a second stack portion spaced apart from each other by the recess, each of the first stack portion and the second stack portion including a plurality of sacrificial features and a plurality of channel features alternately stacked over each other;
• and
• forming a source/drain feature in the recess, the source/drain feature interfacing a sidewall of each of the plurality of channel features, a thickness of the source/drain feature being different from a width of the source/drain feature in a cross-sectional view, the source/drain feature having a p-type conductivity, being doped with a dopant, and including a seed layer adjacent the sidewall of the each of the plurality of channel features, and a p-type epitaxial layer away from the sidewall of the each of the plurality of channel features and covered by the seed layer, the seed layer being formed as a continuous layer covering lateral surfaces of the plurality of sacrificial features and the plurality of channel features.

A semiconductor device, comprising:

• a substrate including a protrusion;
• a plurality of first channel features and a plurality of second channel features disposed on the protrusion of the substrate;
• a first metal gate disposed to surround the plurality of first channel features and including a first gate dielectric layer;
• a second metal gate disposed to surround the plurality of second channel features and including a second gate dielectric layer;
• a pair of first gate spacers laterally covering the first metal gate, a thickness of the pair of first gate spacers being greater than a thickness of the first gate dielectric layer;
• a pair of second gate spacers laterally covering the second metal gate, a thickness of the second gate dielectric layer being less than a thickness of the pair of second gate spacers;
• a source/drain region disposed between the plurality of first channel features and the plurality of second channel features, and including a source/drain feature having a p-type conductivity, the source/drain feature including a seed layer, which is formed as a continuous layer covering lateral surfaces of the plurality of first channel features and the plurality of second channel features;
• an etch stop layer disposed over the source/drain region;
• and
• an interlayer dielectric disposed over the etch stop layer,
• a portion of the etch stop layer extending along a sidewall of each of the pair of first gate spacers and the pair of second gate spacers, such that each of the pair of first gate spacers is between the first metal gate and the etch stop layer, and each of the pair of second gate spacers is between the second metal gate and the etch stop layer.