Methods of forming gate structures by a gate-cut-last process and the resulting structures

A method, comprising:

• forming an uncut line-type gate structure above first and second spaced-apart active regions of a semiconductor substrate and above an isolation region formed in said substrate that is positioned between said first and second spaced-apart active regions, wherein said uncut line-type gate structure comprises a gate electrode structure and a gate cap layer positioned above said gate electrode structure and wherein said line-type gate structure has been patterned so as to have a desired critical dimension of a transistor device;
• forming a sidewall spacer around a perimeter of said line-type gate structure;
• forming a layer of insulating material above said line-type gate structure, said isolation region and said first and second spaced-apart active regions;
• performing a planarization process on said layer of insulating material so as to expose an upper surface of said gate cap layer;
• forming a patterned gate cut mask above said substrate, wherein said patterned gate cut mask has an opening formed therein that is positioned above said isolation region and exposes an axial portion of said gate cap layer;
• performing at least one etching process through said opening in said gate cut mask to remove said exposed axial portion of said gate cap layer and an axial portion of said gate electrode so as to thereby define first and second cut ends of first and second gate electrodes, respectively, and an isolation plug cavity positioned between said sidewall spacer and said first and second cut ends of said first and second gate electrodes;
• and
• forming a gate cut isolation plug in said isolation plug cavity.

An integrated circuit product, comprising:

• first and second spaced-apart active regions defined in a semiconductor substrate;
• an isolation region formed in said substrate between said first and second spaced-apart active regions;
• first and second spaced-apart gate electrodes positioned above said first and second active regions, respectively, said first and second gate electrode structures comprising opposing first and second cut end surfaces, respectively;
• a sidewall spacer that is positioned adjacent sidewalls of said first and second spaced-apart gate electrodes, wherein said sidewall spacer extends across said isolation region;
• and
• a gate cut isolation plug having first, second, third and fourth sides, wherein said first side and said second side each contact one of said first and second cut end surfaces, and wherein said third side and said fourth side each contact a portion of said sidewall spacer that extends across said isolation region.

An integrated circuit product, comprising:

• first and second spaced-apart active regions defined in a semiconductor substrate;
• an isolation region formed in said substrate between said first and second spaced-apart active regions;
• first and second spaced-apart gate electrodes positioned above said first and second active regions, respectively, said first and second gate electrode structures comprising opposing first and second cut end surfaces, respectively;
• a sidewall spacer that is positioned adjacent sidewalls of said first and second spaced-apart gate electrodes;
• a layer of insulating material that is positioned above said substrate and said isolation region;
• and
• a gate cut isolation plug having first, second, third and fourth sides, wherein said first side and said second side each contact one of said first and second cut end surfaces, and wherein said third side and said fourth side each contact a portion of said layer of insulating material positioned above said isolation region.