Air gap spacer between contact and gate region
AssigneeInternational Business Machines Corporation
InventorsKangguo Cheng, Nicolas Jean Loubet, Xin Miao, Alexander Reznicek
Life of this patent
Estimating the term…
Abstract
Unfilled gaps are provided as spacers between gate stacks and electrically conductive source/drain contacts to reduce parasitic capacitance in CMOS structures. Sidewall spacers are removed partially or entirely from portions of the gate stacks and replaced by materials such as amorphous semiconductor materials. Source/drain contacts subsequently formed on source/drain regions adjoin the spacer replacement material. Selective removal of the spacer replacement material leaves unfilled gaps between the source/drain contacts and the gate stacks. The unfilled gaps are then sealed by a dielectric layer that leaves the gaps substantially unfilled.
Claims19
A method comprising:
- obtaining a structure including:
- a plurality of field-effect transistors, each field-effect transistor including a channel region, a gate stack adjoining the channel region, source/drain regions adjoining the channel region, and sidewall spacers lining first and second sidewalls of the gate stack,
- a dielectric layer overlying the gate stacks, and
- trenches within the dielectric layer, the trenches exposing a plurality of the sidewall spacers and a plurality of the source/drain regions;
- removing the sidewall spacers at least in part from at least one of the first and second sidewalls of a plurality of the gate stacks;
- replacing the removed sidewall spacers with dummy spacers;
- forming electrically conductive source/drain contacts on a plurality of the source/drain regions and between pairs of the dummy spacers;
- and
- removing the dummy spacers, thereby forming unfilled gaps between the source/drain contacts and the gate stacks.
A semiconductor structure comprising:
- a plurality of field-effect transistors, each field-effect transistor including a channel region, a gate stack adjoining the channel region, and source/drain regions adjoining the channel region;
- a dielectric layer overlying the gate stacks;
- a plurality of trenches within the dielectric layer;
- electrically conductive source/drain contacts within the trenches and on a plurality of the source/drain regions;
- the source/drain contacts and the gate stacks being separated by unfilled gaps, the unfilled gaps including sealed upper end portions;
- wherein each of the gate stacks includes a first sidewall, a sidewall spacer on the first sidewall, a second sidewall, a sidewall dielectric layer on the second sidewall, the sidewall spacer having a greater thickness than the sidewall dielectric layer, the unfilled gap adjoining the sidewall dielectric layer.
Dependencies are inferred from the claim text.