Vertical metal liners for gate merge in sequential fets

A stacked field effect transistor (FET) device, comprising:

• a lower FET, an upper FET disposed over the lower FET in a vertically mis-aligned formation, and oxide vertically interposed between the lower FET and the upper FET,
• wherein the lower FET comprises lower gate metal surrounding semiconductor channels and a self-aligned contact (SAC) cap disposed over the lower gate metal, and wherein the upper FET comprises upper gate metal surrounding semiconductor channels;
• and
• a gate merge connection comprising:
• a metal plug disposed in the SAC cap in contact with the lower gate metal;
• and
• a conformal metal liner disposed as a liner along the upper gate metal, the oxide, and the SAC cap and in contact with the metal plug.

A stacked field effect transistor (FET) device fabrication method, comprising:

• forming a lower FET comprising lower gate metal surrounding semiconductor channels and a self-aligned contact (SAC) cap disposed over the lower gate metal;
• disposing a metal plug in the SAC cap and in contact with the lower gate metal;
• disposing oxide over the lower FET, the SAC cap, and the metal plug;
• forming, over the oxide in a vertically misaligned formation with the lower FET, an upper FET comprising upper gate metal surrounding semiconductor channels;
• executing gate cut patterning to expose the SAC cap and the metal plug;
• and
• forming a metal liner along the upper gate metal and the oxide and in contact with the metal plug.