Interconnect inner spacer configurations

A method comprising:

• providing a semiconductor structure having a stack of dielectric layers comprising a first insulating layer and a second insulating layer above the first insulating layer;
• forming a plurality of sacrificial mandrel features on top of the second insulating layer;
• forming a spacer layer by depositing spacer material conformally around the sacrificial mandrel features;
• performing a mandrel pull-back process to remove at least a first sacrificial mandrel feature of the plurality of sacrificial mandrel features, wherein the removed first sacrificial mandrel feature is adjacent to a non-mandrel line comprising a first placeholder layer;
• adjusting a thickness of sidewalls of the spacer layer exposed by the mandrel pull-back process, wherein the adjusting comprises depositing additional spacer material conformally around the spacer layer;
• etching continuity line openings into at least the first insulating layer;
• and
• forming metal lines in at least a portion of the continuity line openings.

A semiconductor structure comprising:

• a substrate;
• a dielectric interconnect layer positioned on top of the substrate;
• a plurality of metal lines positioned in the dielectric interconnect layer;
• a self-aligned mandrel cut region in a first metal line of the plurality of metal lines;
• and
• a self-aligned non-mandrel cut region in a second metal line of the plurality of metal lines, wherein a first spacing between the first metal line and a third metal line adjacent to the first metal line is different than a second spacing between the second metal line and a fourth metal line adjacent to the second metal line.