Field effect transistor with inner spacer liner layer and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTsung-Han Chuang, Zhi-Chang Lin, Shih-Cheng Chen, Jung-Hung Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
Life of this patent
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Abstract
A device includes a substrate, a first nanostructure channel above the substrate and a second nanostructure channel between the first nanostructure channel and the substrate. An inner spacer is between the first nanostructure channel and the second nanostructure channel. A gate structure abuts the first nanostructure channel, the second nanostructure channel and the inner spacer. A liner layer is between the inner spacer and the gate structure.
Claims20
A device, comprising:
- a nanostructure channel;
- an inner spacer above or below the nanostructure channel;
- a gate structure abutting the nanostructure channel and the inner spacer;
- and
- a liner layer between the inner spacer and the gate structure, the liner layer and the nanostructure channel include substantially the same material.
A device comprising:
- a semiconductor nanosheet;
- a first inner spacer above the semiconductor nanosheet;
- a second inner spacer below the semiconductor nanosheet;
- a first liner layer between the semiconductor nanosheet and the first inner spacer;
- and
- a second liner layer between the semiconductor nanosheet and the second inner spacer,
- wherein each of the first liner layer and the second liner layer includes a semiconductive material.
A method, comprising:
- forming a vertical stack of alternating first nanosheets and second nanosheets over a substrate;
- forming recesses by removing end portions of the second nanosheets;
- and
- forming a liner layer in the recesses, including:
- depositing a semiconductive material in the recesses;
- and
- forming an inner spacer in each of the recesses.
Dependencies are inferred from the claim text.