H10D 64/01326
Aspects related to lithography, isolation or planarisation of the conductor
Official title: {Aspects related to lithography, isolation or planarisation of the conductor}
H10D64/01326 (Aspects related to lithography, isolation or planarisation of the conductor) appears on 2,027 US grants and 1,849 published applications in this corpus.
Search patents in H10D- Granted patents
- 2,027
- Published applications
- 1,849
- Assignees
- 327
- Inventors
- 3,344
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 2 | 0 |
| 1978 | 1 | 0 |
| 1979 | 1 | 0 |
| 1980 | 0 | 0 |
| 1981 | 1 | 0 |
| 1982 | 5 | 0 |
| 1983 | 2 | 0 |
| 1984 | 6 | 0 |
| 1985 | 5 | 0 |
| 1986 | 2 | 0 |
| 1987 | 5 | 0 |
| 1988 | 10 | 0 |
| 1989 | 3 | 0 |
| 1990 | 4 | 0 |
| 1991 | 13 | 0 |
| 1992 | 9 | 0 |
| 1993 | 5 | 0 |
| 1994 | 8 | 0 |
| 1995 | 14 | 0 |
| 1996 | 8 | 0 |
| 1997 | 20 | 0 |
| 1998 | 35 | 0 |
| 1999 | 62 | 0 |
| 2000 | 76 | 0 |
| 2001 | 85 | 27 |
| 2002 | 71 | 65 |
| 2003 | 73 | 58 |
| 2004 | 71 | 76 |
| 2005 | 55 | 71 |
| 2006 | 53 | 68 |
| 2007 | 49 | 65 |
| 2008 | 38 | 74 |
| 2009 | 41 | 68 |
| 2010 | 60 | 121 |
| 2011 | 75 | 74 |
| 2012 | 105 | 67 |
| 2013 | 64 | 71 |
| 2014 | 79 | 104 |
| 2015 | 91 | 107 |
| 2016 | 107 | 76 |
| 2017 | 88 | 82 |
| 2018 | 76 | 80 |
| 2019 | 73 | 66 |
| 2020 | 90 | 92 |
| 2021 | 58 | 64 |
| 2022 | 58 | 57 |
| 2023 | 42 | 58 |
| 2024 | 44 | 68 |
| 2025 | 48 | 64 |
| 2026 | 36 | 26 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Integrated circuit structures with cavity spacers6 Oct 2026US 12,757,473 B2Intel Corporation
- Inverted gate cut region29 Sep 2026US 12,751,063 B2International Business Machines Corporation
- Semiconductor device and manufacturing method thereof15 Sep 2026US 12,740,120 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Gate contacts for semiconductor devices8 Sep 2026US 12,733,252 B2International Business Machines Corporation
- Gate cuts with self-forming polymer layer25 Aug 2026US 12,720,835 B2Intel Corporation
- Large dimension metal gate field-effect transistor (fet) with metal gate dummy structures8 Oct 2026US 2026/0314024 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Trench isolation with conductive structures8 Oct 2026US 2026/0314033 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Method of manufacturing a semiconductor device including isolation structures24 Sep 2026US 2026/0293301 A1Samsung Electronics Co., Ltd.
- Method for forming semiconductor structure17 Sep 2026US 2026/0282441 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor device structure with gate stack17 Sep 2026US 2026/0282482 A1Taiwan Semiconductor Manufacturing Company.Ltd
Most cited
By later US patents
- Selective photoresist hardening to facilitate lateral trimming537US 6,716,571 B2Advanced Micro Devices, Inc. · 2004
- Method of trimming technology529US 7,354,847 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2008
- Integration of absorption based heating bake methods into a photolithography track system470US 9,613,801 B2Tokyo Electron Limited · 2017
- Method for fabricating a gate structure of a field effect transistor409US 6,924,191 B2APPLIED Materials.Inc. · 2005
- Fabrication process of sub-micrometer channel length MOSFETs281US 4,419,809 AInternational Business Machines Corporation · 1983