Semiconductor device and manufacturing method thereof

A fabrication method, comprising:

• forming a gate stack in an area previously occupied by a dummy gate structure;
• forming a first metal cap layer over the gate stack;
• forming a first dielectric cap layer over the first metal cap layer;
• selectively removing a portion of the gate stack and the first metal cap layer while leaving a sidewall portion of the first metal cap layer that extends along a sidewall of the first dielectric cap layer;
• forming a second metal cap layer over the gate stack and the first metal cap layer wherein a sidewall portion of the second metal cap layer extends further along a sidewall of the first dielectric cap layer;
• forming a second dielectric cap layer over the second metal cap layer;
• and
• flattening a top layer of the first dielectric cap layer and the second dielectric cap layer using planarization operations.

A fabrication method, comprising:

• forming a gate stack in an area previously occupied by a dummy gate structure;
• forming a first metal cap layer over the gate stack;
• forming a first dielectric cap layer over the first metal cap layer;
• selectively removing a portion of the gate stack and the first metal cap layer while leaving a sidewall portion of the first metal cap layer that extends along a sidewall of the first dielectric cap layer;
• forming a second metal cap layer over the gate stack and the first metal cap layer, the forming comprising forming a combined metal cap layer comprising the first metal cap layer and the second metal cap layer, wherein the combined metal cap layer is at a height at a sidewall portion of the combined metal cap layer that is higher than a height of the sidewall portion of the first metal cap layer, and wherein the sidewall portion of the combined metal cap layer has a length (Linner) that is longer than a length (Louter) at an end portion of the combined metal cap layer that borders a gate spacer;
• forming a second dielectric cap layer over the combined metal cap layer, the forming comprising forming a combined dielectric cap layer comprising the first dielectric cap layer and the second dielectric cap layer;
• and
• flattening a top layer of the combined dielectric cap layer using planarization operations.