Semiconductor device structure with gate stack

A semiconductor device structure, comprising:

• a first nanostructure and a second nanostructure;
• a first gate stack wrapped around the first nanostructure;
• a second gate stack wrapped around the second nanostructure;
• a dielectric layer over the first gate stack and the second gate stack;
• and
• a dielectric structure passing through the dielectric layer and between the first gate stack and the second gate stack, wherein the dielectric structure has a void between the first nanostructure and the second nanostructure.

A semiconductor device structure, comprising:

• a first nanostructure and a second nanostructure;
• a first gate stack wrapped around the first nanostructure;
• a second gate stack wrapped around the second nanostructure;
• a dielectric layer over the first gate stack and the second gate stack;
• an isolation structure in the dielectric layer, wherein the isolation structure divides the dielectric layer into a first part and a second part respectively over the first gate stack and the second gate stack;
• a dielectric structure passing through the dielectric layer and the isolation structure and between the first gate stack and the second gate stack;
• and
• a spacer layer between the dielectric structure and the dielectric layer and between the dielectric structure and the isolation structure.