Gate cuts with self-forming polymer layer

An electronic device, comprising:

• a chip package comprising one or more dies, at least one of the one or more dies comprising
• a first semiconductor device having a first semiconductor region extending in a first direction from a first source or drain region to a second source or drain region, and a first gate structure extending in a second direction over the first semiconductor region;
• a second semiconductor device having a second semiconductor region extending in the first direction from a third source region to a fourth source or drain region, and a second gate structure extending in the second direction over the second semiconductor region;
• and
• a cut structure extending in the first direction between and separating the first source or drain region and the third source or drain region, the cut structure comprising a polymer layer at edges of the cut structure and a dielectric material on the polymer layer, such that the polymer layer is directly on at least a portion of the first source or drain region.

An integrated circuit comprising:

• one or more semiconductor regions extending in a first direction between corresponding source or drain regions;
• a gate structure extending in a second direction over the one or more semiconductor regions;
• and
• a gate cut extending in a third direction through an entire thickness of the gate structure, the gate cut comprising a polymer layer at edges of the gate cut and a dielectric material on the polymer layer, wherein the gate cut further extends in the first direction adjacent to at least one of the source or drain regions, and wherein the polymer layer is directly on at least a portion of the at least one of the source or drain regions.