Gate contacts for semiconductor devices

A monolithic semiconductor structure, comprising:

• a device layer including a front side and a back side, the device layer comprising:
• field-effect transistors within a front side interlevel dielectric layer, each of the field-effect transistors including a channel region, a gate stack adjoining the channel region, and first and second source/drain regions extending laterally from the channel region;
• a gate cut region between a first gate stack of a first one of the field-effect transistors and a second gate stack of a second one of the field-effect transistors;
• a dielectric fill within the gate cut region, the dielectric fill comprising a first dielectric compound;
• a dielectric liner within the gate cut region and adjoining the first gate stack, the second gate stack, and the dielectric fill, the dielectric liner comprising a second dielectric compound, the second dielectric compound having a different composition than the first dielectric compound;
• a back-end-of-line interconnect layer over the front side of the device layer, the back-end-of-line interconnect layer being electrically connected to the device layer;
• a metal layer between the device layer and the back-end-of-line interconnect layer, the metal layer comprising signal tracks within a middle-of-line interlevel dielectric layer;
• and
• a gate contact electrically connecting one of the first gate stack and the second gate stack to a first signal track within the metal layer, the gate contact comprising:
• a bottom portion extending within the gate cut region and directly contacting one of the first gate stack and the second gate stack, the bottom portion of the gate contact being positioned between a vertical side wall of the one of the first gate stack and the second gate stack and the dielectric fill and adjoining a top surface of the dielectric liner;
• and
• a top portion extending vertically from the bottom portion and electrically connected to the first signal track.

A method of forming a gate contact for a field-effect transistor, comprising:

• obtaining a device layer comprising a plurality of transistor channel regions and a gate stack extending across the transistor channel regions, the gate stack comprising a metal gate portion and a gate dielectric layer between the metal gate portion and the transistor channel regions;
• forming a gate cut trench through the gate stack;
• forming a dielectric liner within the gate cut trench;
• forming a dielectric fill within the gate cut trench over the dielectric liner;
• forming a middle-of-line interlevel dielectric layer over the device layer;
• patterning the middle-of-line interlevel dielectric layer, thereby forming a gate contact opening over a portion of the gate cut region;
• selectively recessing the dielectric liner with respect to the dielectric fill, thereby exposing a vertical end portion of the gate stack and forming a space extending downwardly from the gate contact opening and between the dielectric fill and the vertical end portion of the gate stack;
• and
• filling the gate contact opening and the space with contact metal.