Method of trimming technology

A method of forming a gate electrode in a MOSFET, comprising:

• providing a substrate with isolation regions formed therein and with a gate stack comprised of a gate layer on a gate dielectric layer formed on said substrate between said isolation regions;
• forming a bilayer stack comprised of a top photoresist layer and an organic underlayer on said gate layer, said organic underlayer is thicker than said top photoresist layer;
• forming a pattern having a feature with a first width in said top photoresist layer;
• transferring said pattern through the organic underlayer with a first plasma etch step to produce a pattern that has a feature with a first width and sidewalls;
• trimming said pattern in said top photoresist and organic underlayer with a second plasma etch step to give a pattern in the bilayer stack having a feature with a second width and sidewalls, said second width is smaller than said first width;
• and
• transferring said trimmed pattern with said second width through said gate layer with a third plasma etch step to form a gate electrode.

A method of forming a gate electrode in a MOSFET, comprising:

• providing a substrate with isolation regions formed therein and with a gate stack comprised of a gate layer on a gate dielectric layer formed on said substrate between said isolation regions;
• forming a bilayer stack comprised of a top photoresist layer with a surface region and an organic underlayer on said gate layer, said organic underlayer is thicker than said top photoresist layer;
• patternwise exposing a surface region of the top photoresist layer;
• selectively silylating portions of the top photoresist layer to give silylated portions having a first width;
• forming a pattern having a feature with a first width in said top photoresist layer by a first plasma etch step that removes non-silylated portions in the surface region and the underlying top photoresist layer;
• transferring said pattern through the organic underlayer with a second plasma etch step, said pattern has a feature with sidewalls and a first width;
• trimming said pattern in said top photoresist layer and organic underlayer with a third plasma etch step to give a pattern in the bilayer stack having a feature with sidewalls and a second width, said second width is smaller than said first width;
• transferring said trimmed pattern with said second width through said gatelayer with a fourth plasma etch step to form a gate electrode having a second width.