H10D 30/673
Characterised by the shapes, relative sizes or dispositions of the gate electrodes
Official title: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
H10D30/673 (Characterised by the shapes, relative sizes or dispositions of the gate electrodes) appears on 14,805 US grants and 19,006 published applications in this corpus.
Search patents in H10D- Granted patents
- 14,805
- Published applications
- 19,006
- Assignees
- 1,051
- Inventors
- 13,382
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 1 | 0 |
| 1978 | 0 | 0 |
| 1979 | 1 | 0 |
| 1980 | 4 | 0 |
| 1981 | 7 | 0 |
| 1982 | 4 | 0 |
| 1983 | 4 | 0 |
| 1984 | 3 | 0 |
| 1985 | 3 | 0 |
| 1986 | 9 | 0 |
| 1987 | 14 | 0 |
| 1988 | 17 | 0 |
| 1989 | 9 | 0 |
| 1990 | 13 | 0 |
| 1991 | 33 | 0 |
| 1992 | 38 | 0 |
| 1993 | 36 | 0 |
| 1994 | 45 | 0 |
| 1995 | 42 | 0 |
| 1996 | 67 | 0 |
| 1997 | 73 | 0 |
| 1998 | 114 | 0 |
| 1999 | 97 | 0 |
| 2000 | 100 | 0 |
| 2001 | 136 | 88 |
| 2002 | 183 | 256 |
| 2003 | 235 | 274 |
| 2004 | 247 | 368 |
| 2005 | 252 | 436 |
| 2006 | 289 | 331 |
| 2007 | 272 | 352 |
| 2008 | 261 | 278 |
| 2009 | 266 | 262 |
| 2010 | 308 | 230 |
| 2011 | 242 | 317 |
| 2012 | 265 | 315 |
| 2013 | 303 | 301 |
| 2014 | 369 | 429 |
| 2015 | 470 | 648 |
| 2016 | 680 | 952 |
| 2017 | 896 | 1043 |
| 2018 | 912 | 1004 |
| 2019 | 1034 | 989 |
| 2020 | 886 | 986 |
| 2021 | 786 | 1006 |
| 2022 | 781 | 1275 |
| 2023 | 768 | 1634 |
| 2024 | 1004 | 1833 |
| 2025 | 1231 | 2313 |
| 2026 | 995 | 1086 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Semiconductor memory devices with dielectric fin structures6 Oct 2026US 12,755,790 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Selective deposition of gate dielectric layer of semiconductor device and the semiconductor device manufactured thereby6 Oct 2026US 12,757,424 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Conductive bridge through dielectric wall between source or drain contacts6 Oct 2026US 12,757,439 B2Intel Corporation
- Semiconductor structure and method for forming the same6 Oct 2026US 12,757,440 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Contact formation with staggered gate patterning6 Oct 2026US 12,757,441 B2International Business Machines Corporation
- Display device8 Oct 2026US 2026/0311650 A1Samsung Display Co., Ltd.
- Semiconductor device8 Oct 2026US 2026/0311745 A1Semiconductor Energy Laboratory Co.Ltd.
- Semiconductor structure and method for manufacturing the same8 Oct 2026US 2026/0313867 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Multi-channel ferroelectric memory structure8 Oct 2026US 2026/0313908 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Three dimensional semiconductor device with memory stack8 Oct 2026US 2026/0313917 A1Taiwan Semiconductor Manufacturing Company.Ltd
Most cited
By later US patents
- Semiconductor device4,046US 7,297,977 B2Hewlett-Packard Development Company, L. P. · 2007
- Combined binary oxide semiconductor device3,995US 7,282,782 B2Hewlett-Packard Development Company, L. P. · 2007
- Indium oxide-based thin film transistors and circuits3,962US 7,211,825 B22007
- Transistor using an isovalent semiconductor oxide as the active channel layer3,960US 7,462,862 B2Hewlett-Packard Development Company, L. P. · 2008
- MOSFET having a double gate1,461US 6,646,307 B1Advanced Micro Devices, Inc. · 2003