Semiconductor structure and method for manufacturing the same

A semiconductor structure, comprising:

• a first pull-down transistor and a first pull-up transistor vertically stacked and sharing a first gate structure extending lengthwise in a first direction, wherein the first pull-down transistor and the first pull-up transistor comprise semiconductor layers extending in a second direction different from the first direction;
• a first pass-gate transistor having a second gate structure extending lengthwise in the first direction, wherein the first gate structure is separated from the second gate structure in the first direction;
• a second pull-down transistor and a second pull-up transistor vertically stacked and sharing a third gate structure extending lengthwise in the first direction;
• a second pass-gate transistor having a fourth gate structure extending lengthwise in the first direction, wherein the third gate structure is separated from the fourth gate structure in the first direction;
• a first connection structure vertically overlapping the first gate structure and the second gate structure, wherein the first connection structure is electrically connected to the first gate structure and is separated from the second gate structure;
• a second connection structure vertically overlapping the third gate structure and the fourth gate structure, wherein the second connection structure is electrically connected to the third gate structure and is separated from the fourth gate structure;
• a first butt contact vertically overlapping the first connection structure, the second gate structure, and a source/drain feature between the second gate structure and the third gate structure;
• a second butt contact vertically overlapping the second connection structure, the fourth gate structure, and a source/drain feature between the first gate structure and the fourth gate structure;
• a contact etch stop layer over the source/drain feature between the second gate structure and the third gate structure;
• and
• a gate spacer between the second gate structure and the contact etch stop layer.

A method for manufacturing a semiconductor structure, comprising:

• forming a first fin and a second fin extending in a first direction and arranged in a second direction different from the first direction, wherein the first fin and second fin comprise first semiconductor layers and second semiconductor layers over the first semiconductor layers;
• forming an isolation structure between the first fin and the second fin in the second direction;
• forming a first gate structure and a second gate structure extending in the second direction and over the first fin and the second fin;
• forming a first dielectric structure in the first gate structure to cut the first gate structure into a third gate structure and a fourth gate structure;
• forming a second dielectric structure in the second gate structure to cut the second gate structure into a fifth gate structure and a sixth gate structure;
• forming a first pull-down transistor comprising the third gate structure and the first semiconductor layers, a first pull-up transistor comprising the third gate structure and the second semiconductor layers, a first pass-gate transistor comprising the fourth gate structure and the first semiconductor layers, and a first dummy transistor comprising the fourth gate structure and the second semiconductor layers, wherein the first pull-down transistor and the first pull-up transistor are vertically stacked, wherein the first pass-gate transistor and the first dummy transistor are vertically stacked;
• forming a second pull-down transistor comprising the sixth gate structure and the first semiconductor layers, a second pull-up transistor comprising the sixth gate structure and the second semiconductor layers, a second pass-gate transistor comprising the fifth gate structure and the first semiconductor layers, and a second dummy transistor comprising the fifth gate structure and the second semiconductor layers, wherein the second pull-down transistor and the second pull-up transistor are vertically stacked, wherein the second pass-gate transistor and the second dummy transistor are vertically stacked;
• forming a first connection structure interfacing the sixth gate structure and a second connection structure interfacing the third gate structure;
• and
• forming a first butt contact vertically overlapping the first connection structure and the fifth gate structure and a second butt contact vertically overlapping the second connection structure and the fourth gate structure.