Selective deposition of gate dielectric layer of semiconductor device and the semiconductor device manufactured thereby

A method for manufacturing a semiconductor device, comprising:

• forming a semiconductor structure on a substrate, the semiconductor structure including:
• a pair of source/drain regions spaced apart from each other,
• a plurality of nanosheet segments connected between the pair of source/drain regions and spaced apart from each other in a vertical direction perpendicular to the substrate,
• a plurality of interfacial layers respectively disposed on the plurality of nanosheet segments and including a nitrogen-free dielectric material, and
• a pair of spacers extending upwardly from the plurality of nanosheet segments in the vertical direction and spaced apart from each other so as to define a void between the pair of spacers, the pair of spacers including a nitrogen-containing dielectric material;
• forming a blocking layer to cover side surfaces of the pair of spacers facing the void by subjecting the nitrogen-containing dielectric material to an azidation reaction with an azide compound and a click reaction with a plurality of precursor molecules, one of which includes a head group containing an alkyne radical and a tail group connected to the head group;
• forming a gate dielectric layer on the plurality of interfacial layers so as to surround the plurality of nanosheet segments;
• removing the blocking layer;
• and
• forming a metal filling layer which fills the void so as to be in direct contact with the pair of spacers, and which surrounds the plurality of nanosheet segments and is separated from the plurality of nanosheet segments by the gate dielectric layer and the plurality of interfacial layers.

A method for manufacturing a semiconductor device, comprising:

• forming a semiconductor structure on a substrate, the semiconductor structure including:
• a first source/drain region and a second source/drain region spaced apart from each other in a first direction parallel to a bottom surface of the substrate,
• a channel region disposed between the first source/drain region and the second source/drain region in the first direction,
• a first spacer and a second spacer extending upwardly from the channel region in a second direction different from the first direction and spaced apart from each other in the first direction so as to define a void between the first spacer and the second spacer, the first spacer and the second spacer including a first nitrogen-containing dielectric material, and
• an etch stop layer including a first etch stop layer portion and a second etch stop layer portion which extend upwardly in the second direction from the first source/drain region and the second source, respectively, and which are laterally covered by the first spacer and the second spacer, respectively, the etch stop layer including a second nitrogen-containing dielectric material;
• forming a blocking layer to cover a first side surface of the first spacer and a second side surface of the second spacer facing the void and to cover an upper surface of one of the first etch stop layer portion and the second etch stop layer portion by subjecting the first nitrogen-containing dielectric material and the second nitrogen-containing dielectric material to an azidation reaction with an azide compound and a click reaction with a plurality of precursor molecules, one of which includes a head group containing an alkyne radical and a tail group connected to the head group;
• forming a gate dielectric layer surrounding the channel region;
• removing the blocking layer;
• and
• forming a metal filling layer which fills the void so as to be in direct contact with the first spacer and the second spacer, and which surrounds the channel region and is separated from the channel region by the gate dielectric layer.