US 2026/0311745 A1Published application

Semiconductor device

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsYuki OKAMOTO, Yusuke KOUMURA

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Abstract

A novel semiconductor device is provided. The memory cell includes a first transistor and a first capacitor. A gate of the first transistor is electrically connected to a word line. One of a source and a drain of the first transistor is electrically connected to one terminal of the first capacitor. The other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor and one of a source and a drain of the third transistor. One of a source and a drain of the second transistor and the other of the source and the drain of the third transistor are electrically connected to the second sensing circuit through a bit line. The second sensing circuit has a function of outputting first data corresponding to a potential of the bit line. The memory circuit has a function of retaining second data corresponding to the number of times the memory cell is accessed. The input/output circuit has a function of, in accordance with the second data, determining whether to invert or not to invert the first data and outputting the first data.

Claims9

Dependent claims

A semiconductor device comprising:

a memory cell, a first sensing circuit, a second sensing circuit, an input/output circuit, and a memory circuit,
wherein the memory cell comprises a first transistor and a first capacitor,
wherein the first sensing circuit comprises a second transistor and a third transistor,
wherein a gate of the first transistor is electrically connected to a word line,
wherein one of a source and a drain of the first transistor is electrically connected to one terminal of the first capacitor,
wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor and one of a source and a drain of the third transistor,
wherein one of a source and a drain of the second transistor and the other of the source and the drain of the third transistor are electrically connected to the second sensing circuit through a bit line,
wherein the second sensing circuit is configured to output first data corresponding to a potential of the bit line,
wherein the memory circuit is configured to retain second data corresponding to the number of times the memory cell is accessed, and
wherein the input/output circuit is configured to, in accordance with the second data, determine whether to invert or not to invert the first data and output the first data.

7 more elements

A semiconductor device comprising:

a first memory cell, a second memory cell, a first sensing circuit, a second sensing circuit, a third sensing circuit, a fourth sensing circuit, and an input/output circuit,
wherein the first memory cell comprises a first transistor and a first capacitor,
wherein the second memory cell comprises a seventh transistor and a second capacitor,
wherein the first sensing circuit comprises a second transistor and a third transistor,
wherein the third sensing circuit comprises an eighth transistor and a ninth transistor,
wherein a gate of the first transistor and a gate of the seventh transistor are electrically connected to a word line,
wherein one of a source and a drain of the first transistor is electrically connected to one terminal of the first capacitor,
wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor and one of a source and a drain of the third transistor,
wherein one of a source and a drain of the second transistor and the other of the source and the drain of the third transistor are electrically connected to the second sensing circuit through a first bit line,
wherein one of a source and a drain of the seventh transistor is electrically connected to one terminal of the second capacitor,
wherein the other of the source and the drain of the seventh transistor is electrically connected to a gate of the eighth transistor and one of a source and a drain of the ninth transistor,
wherein one of a source and a drain of the eighth transistor and the other of the source and the drain of the ninth transistor are electrically connected to the fourth sensing circuit through a second bit line,
wherein the second sensing circuit u is configured to output first data corresponding to a potential of the first bit line,
wherein the fourth sensing circuit is configured to output second data corresponding to a potential of the second bit line, and
wherein the input/output circuit is configured to, in accordance with the second data, determine whether to invert or not to invert the first data and output the first data.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/482,334Filed 3 Jun 2024
Priority: JP 2023-0956129 Jun 2023
Published: 8 Oct 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

G11C 11/4091
Read-write [R-W] circuits: sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or…
G11C 11/4096
Read-write [R-W] circuits: input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
G11C 11/4097
Read-write [R-W] circuits: bit-line organisation, e.g. bit-line layout, folded bit lines
H10B 12/33
DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells: the capacitor extending under the transistor