H10D 30/0223
Having source and drain regions or source and drain extensions self-aligned to
Official title: {having source and drain regions or source and drain extensions self-aligned to sides of the gate}
H10D30/0223 (Having source and drain regions or source and drain extensions self-aligned to) appears on 6,710 US grants and 5,676 published applications in this corpus.
Search patents in H10D- Granted patents
- 6,710
- Published applications
- 5,676
- Assignees
- 644
- Inventors
- 7,879
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 3 | 0 |
| 1977 | 4 | 0 |
| 1978 | 11 | 0 |
| 1979 | 6 | 0 |
| 1980 | 8 | 0 |
| 1981 | 10 | 0 |
| 1982 | 13 | 0 |
| 1983 | 9 | 0 |
| 1984 | 11 | 0 |
| 1985 | 16 | 0 |
| 1986 | 18 | 0 |
| 1987 | 25 | 0 |
| 1988 | 25 | 0 |
| 1989 | 36 | 0 |
| 1990 | 38 | 0 |
| 1991 | 48 | 0 |
| 1992 | 52 | 0 |
| 1993 | 69 | 0 |
| 1994 | 55 | 0 |
| 1995 | 82 | 0 |
| 1996 | 103 | 0 |
| 1997 | 131 | 0 |
| 1998 | 190 | 0 |
| 1999 | 268 | 0 |
| 2000 | 350 | 0 |
| 2001 | 325 | 70 |
| 2002 | 251 | 207 |
| 2003 | 213 | 155 |
| 2004 | 209 | 274 |
| 2005 | 181 | 416 |
| 2006 | 255 | 409 |
| 2007 | 239 | 389 |
| 2008 | 217 | 417 |
| 2009 | 243 | 325 |
| 2010 | 274 | 251 |
| 2011 | 281 | 281 |
| 2012 | 209 | 292 |
| 2013 | 273 | 255 |
| 2014 | 293 | 246 |
| 2015 | 261 | 296 |
| 2016 | 258 | 229 |
| 2017 | 182 | 155 |
| 2018 | 169 | 134 |
| 2019 | 162 | 169 |
| 2020 | 140 | 146 |
| 2021 | 123 | 120 |
| 2022 | 97 | 113 |
| 2023 | 90 | 114 |
| 2024 | 85 | 81 |
| 2025 | 70 | 86 |
| 2026 | 29 | 46 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Transistor structure and methods of formation6 Oct 2026US 12,757,428 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Manufacturing method of semiconductor structure and semiconductor structure29 Sep 2026US 12,751,069 B2Changxin Jidian (Beijing) Memory Technologies Co., Ltd.
- Threshold voltage modulation by gate height variation22 Sep 2026US 12,745,430 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Photo mask and lithography method using the same25 Aug 2026US 12,721,115 B2Taiwan Semiconductor Manufacturing Company.Ltd
- LDMOS transistor device and method for forming the same4 Aug 2026US 12,701,732 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Doping profile for strained source/drain region8 Oct 2026US 2026/0313975 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor device17 Sep 2026US 2026/0282429 A1Kabushiki Kaisha Toshiba
- Semiconductor device including gate structure27 Aug 2026US 2026/0255589 A1Samsung Electronics Co., Ltd.
- Semiconductor device and method of manufacturing the same27 Aug 2026US 2026/0255628 A1Powerchip Semiconductor Manufacturing Corporation
- Methods of forming semiconductor layer stacks comprising at least a portion of a vertical channel transistor structure20 Aug 2026US 2026/0247877 A1ASM IP Holding B. V.
Most cited
By later US patents
- Active programmable electronic devices for molecular biological analysis and diagnostics1,006US 5,605,662 ANanogen, Inc. · 1997
- Method of forming a multilayer dielectric stack677US 6,627,503 B2Sharp Laboratories of America, Inc. · 2003
- Method for depositing a nanolaminate film by atomic layer deposition616US 6,930,059 B2Sharp Laboratories of America, Inc. · 2005
- Nanolaminate film atomic layer deposition method574US 7,053,009 B2Sharp Laboratories of America, Inc. · 2006
- Low temperature CVD process with selected stress of the CVD layer on CMOS devices559US 7,393,765 B2APPLIED Materials.Inc. · 2008