Photo mask and lithography method using the same

A method, comprising:

• forming a first metal gate stack and a second metal gate stack over a memory region of a substrate;
• forming spacer structures on opposite sidewalls of the first metal gate stack and the second metal gate stack;
• forming a conductive layer covering the first metal gate stack, the second metal gate stack and the spacer structures;
• forming a hard mask layer over the conductive layer;
• forming a photoresist layer over the hard mask layer;
• patterning the photoresist layer to expose a logic region of the substrate, wherein patterning the photoresist layer comprises:
• exposing the photoresist layer to a radiation through a photo mask, wherein the photo mask comprises a plurality of device features in a patterning region of the photo mask and a plurality of sub-resolution assist features in a non-patterning region of the photo mask, the patterning region corresponds to the memory region, the non-patterning region corresponds to the logic region of the substrate, a first portion of the radiation passes through a space between the plurality of sub-resolution assist features is incident on the logic region of the substrate;
• patterning the hard mask layer using the photoresist layer as an etch mask;
• removing the photoresist layer;
• and
• patterning the conductive layer using the hard mask layer an etch mask.

A method, comprising:

• forming a stack comprising a floating gate material, a dielectric film, a control gate film and a hard mask layer over a memory region of a substrate;
• forming a photoresist layer over the substrate to cover the stack;
• patterning the photoresist layer to expose a portion of the stack over the memory region of the substrate and a logic region of the substrate, wherein patterning the photoresist layer comprises:
• exposing the photoresist layer to a radiation through a photo mask, wherein the photo mask comprises:
• a plurality of device features in a patterning region of the photo mask, wherein the patterning region of the photo mask corresponds to the memory region of the substrate;
• and
• a plurality of first assist features in a non-patterning region of the photo mask, wherein the plurality of first assist features are sub-resolution correction features, the non-patterning region of the photo mask corresponds to the logic region of the substrate;
• patterning the stack using the photoresist layer as an etch mask to form a gate stack;
• and
• removing the photoresist layer.