Semiconductor device including gate structure
AssigneeSamsung Electronics Co., Ltd.
InventorsHyebin CHOI, Chansic YOON, Gyuhyun KIL
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Abstract
A semiconductor device includes an active region, a gate dielectric layer on the active region, and a gate electrode disposed on the gate dielectric layer. The gate electrode includes a first conductive pattern on the gate dielectric layer; a second conductive pattern on the first conductive pattern; and a third conductive pattern on the second conductive pattern. A thickness of the second conductive pattern is smaller than a thickness of the first conductive pattern and smaller than a thickness of the third conductive pattern, and a first width of an upper region of the first conductive pattern is smaller than a second width of the second conductive pattern.
Claims20
A semiconductor device, comprising:
- an active region;
- a gate dielectric layer on the active region;
- and
- a gate electrode on the gate dielectric layer,
- wherein the gate electrode includes:
- a first conductive pattern on the gate dielectric layer;
- a second conductive pattern on the first conductive pattern;
- and
- a third conductive pattern on the second conductive pattern,
- wherein a thickness of the second conductive pattern is smaller than a thickness of the first conductive pattern and smaller than a thickness of the third conductive pattern, and
- wherein a first width of an upper region of the first conductive pattern is smaller than a second width of the second conductive pattern.
A semiconductor device, comprising:
- a cell transistor including a cell gate electrode, a cell gate dielectric layer, a first cell source/drain region, and a second cell source/drain region;
- a bit line electrically connected to the first cell source/drain region of the cell transistor;
- and
- a peripheral transistor including a peripheral gate electrode, a peripheral gate dielectric layer, a first peripheral source/drain region, and a second peripheral source/drain region,
- wherein the peripheral gate electrode is at a different level from the cell gate electrode,
- wherein the peripheral gate electrode includes:
- a first conductive pattern on the peripheral gate dielectric layer;
- a second conductive pattern on the first conductive pattern;
- and
- a third conductive pattern on the second conductive pattern,
- wherein a thickness of the second conductive pattern is smaller than a thickness of the first conductive pattern and smaller than a thickness of the third conductive pattern,
- wherein an upper region of the first conductive pattern has a first width,
- wherein the second conductive pattern has a second width,
- wherein the third conductive pattern has a third width,
- wherein a lower region of the first conductive pattern has a fourth width, and
- wherein the first width of the upper region of the first conductive pattern is smaller than the third width of the third conductive pattern.
A semiconductor device, comprising:
- a cell transistor including a cell gate electrode, a cell gate dielectric layer, a first cell source/drain region, and a second cell source/drain region;
- a bit line electrically connected to the first cell source/drain region of the cell transistor;
- a peripheral transistor including a peripheral gate electrode, a peripheral gate dielectric layer, a first peripheral source/drain region, and a second peripheral source/drain region;
- and
- a spacer structure on a side surface of the peripheral gate electrode,
- wherein the peripheral gate electrode is at a different level from the cell gate electrode,
- wherein the peripheral gate electrode includes:
- a lower conductive pattern on the peripheral gate dielectric layer;
- a first conductive pattern on the lower conductive pattern;
- a second conductive pattern on the first conductive pattern;
- and
- a third conductive pattern on the second conductive pattern,
- wherein a thickness of the second conductive pattern is smaller than a thickness of the first conductive pattern and smaller than a thickness of the third conductive pattern,
- wherein the spacer structure includes:
- a first layer in contact with the first conductive pattern;
- and
- a second layer in contact with the third conductive pattern, and
- wherein a material of the first layer is different from a material of the second layer.
Dependencies are inferred from the claim text.