Threshold voltage modulation by gate height variation

A method, comprising:

• receiving a workpiece comprising:
• a first active region, a second active region and a third active region over a substrate,
• a first gate structure over a channel region of the first active region,
• a second gate structure over a channel region of the second active region,
• a third gate structure over a channel region of the third active region, and
• a pair of gate spacers disposed along sidewalls of each of the first gate structure, the second gate structure, and the third gate structure;
• selectively recessing the second gate structure to form a pilot recess;
• after the selectively recessing of the second gate structure, recessing the first gate structure, the second gate structure and the third gate structure to form a first gate recess over the first gate structure, extend the pilot recess to form a second gate recess over the second gate structure, and form a third gate recess over the third gate structure, wherein the recessing etches the pair of gate spacers at a slower rate such that top surfaces of the pair of gate spacers are higher than top surfaces of the first gate structure, the second gate structure and the third gate structure;
• depositing a selective metal layer over the first gate recess, the second gate recess and the third gate recess such that a top surface of the selective metal layer is lower than the top surfaces of the pair of gate spacers;
• depositing a dielectric cap layer over the selective metal layer;
• and
• after the depositing, planarizing the workpiece,
• wherein the first gate structure comprises a gate dielectric layer and a first work function layer over the gate dielectric layer,
• wherein the second gate structure comprises the gate dielectric layer and a second work function layer over the gate dielectric layer,
• wherein the third gate structure comprises the gate dielectric layer and a third work function layer over the gate dielectric layer,
• wherein each of the first work function layer and the second work function layer is an n-type work function metal layer,
• wherein the third work function layer is a p-type work function metal layer.

A method, comprising:

• receiving a workpiece comprising:
• a first active region, a second active region and a third active region over a substrate,
• a gate dielectric layer over a channel region of the first active region, a channel region of the second active region, and a channel region of the third active region,
• a first source/drain feature over a source/drain region of the first active region, a second source/drain feature over a source/drain region of the second active region, and a third source/drain feature over a source/drain region of the third active region, and
• an interlayer dielectric (ILD) layer over the first source/drain feature, the second source/drain feature, and the third source/drain feature;
• depositing a dipole inducing layer over the gate dielectric layer and the ILD layer such that the dipole inducing layer interfaces a top surface of the ILD layer;
• after the depositing of the dipole inducing layer, performing an anneal process to the workpiece;
• after the performing of the anneal process, removing excess of the dipole inducing layer;
• after the removing, depositing a gate electrode layer over the gate dielectric layer over the channel region of the first active region, the channel region of the second active region, and the channel region of the third active region;
• selectively recessing the gate electrode layer and the gate dielectric layer over the channel region of the second active region to form a pilot recess;
• after the selectively recessing, recessing the gate electrode layer and the gate dielectric layer over the channel region of the first active region, the channel region of the second active region, and the channel region of the third active region to form a first gate recess, a second gate recess, and form a third gate recess, respectively;
• depositing a dielectric cap layer over the first gate recess, the second gate recess and the third gate recess;
• and
• after the depositing, planarizing the workpiece,
• wherein the dipole inducing layer comprises aluminum oxide, zirconium oxide, zinc oxide, yttrium oxide, or lanthanum oxide.