H05K 2201/09481
Via in pad
Official title: Via in pad; Pad over filled via
H05K2201/09481 (Via in pad) appears on 564 US grants and 603 published applications in this corpus.
Search patents in H05K- Granted patents
- 564
- Published applications
- 603
- Assignees
- 286
- Inventors
- 1,279
- Latest grant
- 8 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1978 | 2 | 0 |
| 1979 | 0 | 0 |
| 1980 | 1 | 0 |
| 1981 | 1 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 1 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 2 | 0 |
| 1990 | 0 | 0 |
| 1991 | 3 | 0 |
| 1992 | 2 | 0 |
| 1993 | 4 | 0 |
| 1994 | 6 | 0 |
| 1995 | 7 | 0 |
| 1996 | 10 | 0 |
| 1997 | 7 | 0 |
| 1998 | 12 | 0 |
| 1999 | 19 | 0 |
| 2000 | 15 | 0 |
| 2001 | 15 | 4 |
| 2002 | 18 | 10 |
| 2003 | 12 | 16 |
| 2004 | 17 | 19 |
| 2005 | 11 | 24 |
| 2006 | 19 | 29 |
| 2007 | 18 | 32 |
| 2008 | 32 | 62 |
| 2009 | 30 | 53 |
| 2010 | 28 | 30 |
| 2011 | 30 | 24 |
| 2012 | 26 | 21 |
| 2013 | 29 | 17 |
| 2014 | 15 | 22 |
| 2015 | 18 | 15 |
| 2016 | 9 | 11 |
| 2017 | 20 | 9 |
| 2018 | 9 | 14 |
| 2019 | 14 | 8 |
| 2020 | 7 | 17 |
| 2021 | 14 | 9 |
| 2022 | 10 | 29 |
| 2023 | 20 | 30 |
| 2024 | 19 | 24 |
| 2025 | 18 | 38 |
| 2026 | 14 | 36 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Method and apparatus for surface mount connections8 Sep 2026US 12,731,922 B2Ciena Corporation
- Circuit board11 Aug 2026US 12,707,571 B2LG Innotek Co., Ltd.
- Printed circuit board and manufacturing method thereof30 Jun 2026US 12,672,233 B2Samsung Electro-Mechanics Co., Ltd.
- Receptacle assembly and circuit board9 Jun 2026US 12,652,751 B2Yamaichi Electronics Co., Ltd.
- Package substrate and manufacturing method thereof26 May 2026US 12,641,729 B2Zhuhai ACCESS Semiconductor Co., Ltd.
- Wiring substrate and method for manufacturing wiring substrate8 Oct 2026US 2026/0313802 A1Ibiden Co., Ltd.
- Printed circuit board and manufacturing method thereof1 Oct 2026US 2026/0304620 A1LG Electronics Inc.
- Integrated circuit packages having partial pad vertical interconnect access24 Sep 2026US 2026/0292981 A1Intel Corporation
- Multi-layer board17 Sep 2026US 2026/0282226 A1Tong Hsing Electronic Industries, Ltd.
- Hybrid circuit board10 Sep 2026US 2026/0271185 A1Tong Hsing Electronic Industries, Ltd.
Most cited
By later US patents
- Method for forming an interconnect having a penetration limited contact structure for establishing a temporary electrical connection with a semiconductor die241US 5,686,317 AMicron Technology, Inc. · 1997
- Carrier for testing an unpackaged semiconductor die215US 5,541,525 AMicron Technology, Inc. · 1996
- Process for manufacturing a semiconductor package with bi-substrate die214US 5,946,553 AMicron Technology, Inc. · 1999
- Testing apparatus having substrate interconnect for discrete die burn-in for nonpackaged die212US 5,408,190 AMicron Technology, Inc. · 1995
- Method of interconnecting electronic components using a plurality of conductive studs210US 6,258,625 B1International Business Machines Corporation · 2001