G11C 29/12015
Comprising clock generation or timing circuitry
Official title: {comprising clock generation or timing circuitry}
G11C29/12015 (Comprising clock generation or timing circuitry) appears on 724 US grants and 759 published applications in this corpus.
Search patents in G11C- Granted patents
- 724
- Published applications
- 759
- Assignees
- 165
- Inventors
- 1,495
- Latest grant
- 29 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1996 | 1 | 0 |
| 1997 | 0 | 0 |
| 1998 | 1 | 0 |
| 1999 | 6 | 0 |
| 2000 | 3 | 0 |
| 2001 | 1 | 1 |
| 2002 | 8 | 10 |
| 2003 | 15 | 17 |
| 2004 | 19 | 39 |
| 2005 | 20 | 24 |
| 2006 | 26 | 21 |
| 2007 | 22 | 18 |
| 2008 | 20 | 21 |
| 2009 | 17 | 28 |
| 2010 | 22 | 11 |
| 2011 | 17 | 9 |
| 2012 | 13 | 9 |
| 2013 | 8 | 13 |
| 2014 | 17 | 16 |
| 2015 | 21 | 22 |
| 2016 | 25 | 21 |
| 2017 | 34 | 40 |
| 2018 | 38 | 32 |
| 2019 | 32 | 37 |
| 2020 | 41 | 38 |
| 2021 | 41 | 44 |
| 2022 | 61 | 80 |
| 2023 | 66 | 65 |
| 2024 | 49 | 48 |
| 2025 | 48 | 45 |
| 2026 | 32 | 50 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Image display device29 Sep 2026US 12,749,550 B2LG Electronics Inc.
- Unmatched data path delay compensation for non-volatile memory22 Sep 2026US 12,744,099 B2SanDisk Technologies LLC
- Proactive history read adaptation without test read1 Sep 2026US 12,725,673 B2SK hynix Inc.
- Defect detection during erase operations18 Aug 2026US 12,712,041 B2Micron Technology, Inc.
- Variable resistance for current control in nonvolatile memory arrays18 Aug 2026US 12,712,045 B2SanDisk Technologies LLC
- Multiple input signature register circuit with pass-gate exclusive or logic8 Oct 2026US 2026/0311792 A1Micron Technology, Inc.
- Scheduling scan operations in memory sub-systems1 Oct 2026US 2026/0301836 A1Micron Technology, Inc.
- Clock generation circuits for memory devices with built-in self test1 Oct 2026US 2026/0301838 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Memory Array Column Configured as a Monolithic Unit Within an Integrated Circuit Scan Chain24 Sep 2026US 2026/0290483 A1SambaNova Systems, Inc.
- Adjustment to multi-phase clock to reduce skew variation caused by power rail bounce at onset of burst of data17 Sep 2026US 2026/0279478 A1Micron Technology, Inc.
Most cited
By later US patents
- Virtual channel synchronous dynamic random access memory151US 6,473,828 B1NEC Corporation · 2002
- Method and apparatus for a low power self test of a memory subsystem67US 6,067,649 ACompaq Computer Corporation · 2000
- Multiple reference phase locked loop65US 7,902,886 B2Diablo Technologies Inc. · 2011
- Ring oscillator circuit for EDRAM/DRAM performance monitoring60US 6,774,734 B2International Business Machines Corporation · 2004
- Method and apparatus for stress testing integrated circuits using an adjustable AC hot carrier injection source60US 6,815,971 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2004