Adjustment to multi-phase clock to reduce skew variation caused by power rail bounce at onset of burst of data

Abstract

Methods, systems, and devices for adjustment to multi-phase clock to reduce skew variation caused by power rail bounce at an onset of a burst of data are described. In accordance with examples as described herein, a memory system may be configured to reduce skew variations between a multi-phase clock and a differential clock caused by power rail bounce during a burst write operation. The memory system may include circuitry including a block of detection/pulse generation circuitry configured to detect a leading phase of the multi-phase clock at an onset of a burst write operation and generate pulse signaling that is indicative of the leading phase. The circuitry may further a block of adder circuitry that is configured to determine, based at least in part on using the pulse signaling, one or more timing adjustments that compensate for the skew variations.

Dependencies are inferred from the claim text.