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US 12,712,041 B2Granted
Defect detection during erase operations
AssigneeMicron Technology, Inc.
InventorsJun Xu, Kitae Park
Life of this patent
Estimating the term…
Abstract
A system includes a memory device including a memory array and processing logic, operatively coupled with the memory array, to perform operations including initiating an erase operation performed with respect to the memory array, identifying, between a pair of components of the memory array, at least one current differential indicative of at least one defect with respect to at least one failure point of the memory array, and causing an indication of the at least one defect to be generated. The erase operation includes a select gate scan sub-operation.
Claims20
A memory device comprising:
- a memory array;
- and
- processing logic, operatively coupled with the memory array, to perform operations comprising:
- initiating an erase operation performed with respect to the memory array, wherein the erase operation comprises a select gate scan sub-operation;
- identifying, between a pair of components of the memory array, at least one current differential indicative of at least one defect with respect to at least one failure point of the memory array;
- and
- causing an indication of the at least one defect to be generated.
4 more elements
A method comprising:
- initiating, by a processing device, an erase operation performed with respect to a memory array of a memory device, wherein the erase operation comprises a select gate scan sub-operation;
- identifying, by the processing device and between a pair of components of the memory array, at least one current differential indicative of at least one defect with respect to at least one failure point of the memory array;
- and
- causing, by the processing device, an indication of the at least one defect to be generated.
1 more element
A system comprising:
- a memory comprising instructions;
- and
- processing logic, operatively coupled with the memory, to perform operations comprising:
- sending, to a memory device, a request to initiate an erase operation performed with respect to a memory array of the memory device, wherein the erase operation comprises a select gate scan sub-operation;
- receiving, from the memory device, an indication of at least one defect with respect to at least one failure point of the memory array, wherein the at least one defect corresponds at least one current differential identified between a pair of components of the memory array;
- and
- in response to receiving the indication of the at least one defect, sending, to the memory device, a request to perform at least one remedial action.
4 more elements
Dependencies are inferred from the claim text.