Memory Array Column Configured as a Monolithic Unit Within an Integrated Circuit Scan Chain

A system comprising:

• an integrated circuit including an array of memory cells arranged in R rows numbered 0 through R−1 and C columns numbered 0 through C−1, a scan chain that includes a column of the array as a monolithic unit, the column comprising M memory cells numbered 0 through M−1, a scan input SI of the column, and a scan output SO of the column, the scan chain further including a scannable element of the integrated circuit that is external to the array and that is coupled with the scan input SI of the column or with the scan output SO of the column;
• a scan input pattern source coupled with the scan chain and configured to drive scan bits into the scan chain;
• and
• a scan output receiver coupled with the scan chain and configured to capture scan bits shifted out of the scan chain;
• wherein the integrated circuit, in a scan shift mode entered upon assertion of a scan enable signal SE, is configured to clock successive memory cells of the column by non-overlapping scan word line SWL pulses asserted on respective rows of memory cells of the column.

A non-transitory computer-readable medium storing instructions that, when executed by a processor of a manufacturing test system, configure the manufacturing test system to:

• assert a scan enable signal SE on an integrated circuit, the integrated circuit including an array of memory cells arranged in R rows numbered 0 through R−1 and C columns numbered 0 through C−1, a column of the array comprising M memory cells numbered 0 through M−1 and being coupled with a scan chain of the integrated circuit as a monolithic unit, the scan chain further including a scannable element of the integrated circuit that is external to the array and that is coupled with a scan input SI of the column or with a scan output SO of the column;
• drive scan bits into the scan chain at the scan input SI of the column from a scan input pattern source of the manufacturing test system;
• and
• clock successive memory cells of the column by asserting non-overlapping scan word line SWL pulses on respective rows of memory cells of the column.