Virtual channel synchronous dynamic random access memory

Abstract

According to one embodiment, a virtual channel synchronous dynamic random access memory (VCSDRAM) (100) can perform a high-frequency test with lower frequency test equipment. The VCSDRAM (100) can include a command decoder circuit (102) that can receive a transfer command and provide a transfer command signal (124). A transfer operation start signal generating circuit (106) can receive and latch the transfer command signal (124). The command decoder circuit (102) can then receive an active command and provide an active command signal (120). The active command signal (120) can result in the generation of a main storage activating signal (128). Having latched the transfer command signal (124), the transfer operation start signal generating circuit (106) can generate a transfer operation start signal (130) in response to the active command signal (120). The transfer operation start signal (130) can generate a control signal (132). In response to the control signal (132), data can be transferred between a main storage portion (114) and a substorage portion (116).

Dependencies are inferred from the claim text.