Unmatched data path delay compensation for non-volatile memory
AssigneeSanDisk Technologies LLC
InventorsJang Woo Lee, Venkatesh Ramachandra, Siddhesh Darne
Life of this patent
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Abstract
In a non-volatile memory system of a memory controller connected to a number of memory dies in which the memory dies use an unmatched architecture for the data input path of the memory dies, the data signals and clock signals from the controller may not align properly when they reach the data latches of the memory die's receiver circuit. To account for possible mis-match, the controller can compensate by individually determining and introducing a corresponding one of multiple relative delay values to the clock signal path. Which delay parameter value is used for each die can be determined based on the power consumed by the memory die when data is transmitted using the different delay values.
Claims20
A non-volatile memory system, comprising:
- a plurality of non-volatile memory dies;
- and
- a non-volatile memory controller comprising:
- a transmitter circuit connected to the plurality of non-volatile memory dies, the transmitter circuit configured to:
- maintain, for each of the memory dies, a corresponding one of a plurality of delay values;
- select one of the memory dies for a data transfer;
- transmit a sequence of data values to the selected memory die;
- transmit a clock signal to the selected memory die for latching the data values of the sequence;
- and
- introduce a corresponding relative delay between the clock signal and the sequence of data values based on the corresponding delay value of the selected memory die.
A method, comprising:
- for each of a plurality of non-volatile memory dies and for each of a plurality of delay values:
- transmitting from a non-volatile memory controller to the non-volatile memory die a sequence of test data values;
- transmitting from the non-volatile memory controller to the non-volatile memory die a clock signal offset from the sequence of test data values by the delay value;
- latching the sequence of test data values in a receiver circuit on the non-volatile memory die using the transmitted clock signal offset by the delay value;
- and
- determining an amount of power consumed latching the sequence of test data values using the transmitted clock signal offset by the delay value;
- and
- for each of the non-volatile memory dies, selecting a corresponding one of the plurality of delay values based on the amount of power consumed latching the sequence of test data values using the transmitted clock signal offset by the plurality of delay values.
A non-volatile memory controller circuit, comprising:
- a transmitter circuit configured to connect to a plurality of memory dies and comprising:
- a clock distribution circuit configured to generate a reference clock signal;
- a data path configured to transmit data values to the plurality of memory dies at a rate of the reference clock signal;
- a clock signal path configured to transmit the reference clock signal to the plurality of memory dies for latching the data values;
- a set of registers configure to store, for each of the memory dies, a corresponding one of a plurality delay values;
- and
- one or more control circuits connected to the data path and the clock signal path and configured to:
- select one of the memory dies for a data transfer;
- transfer a set of data values to the selected memory die over the data path at the rate of the reference clock;
- and
- transfer the reference clock signal to the selected memory die over the clock path at the rate of the reference clock and offset relative to the set of data values by the corresponding delay value of the selected memory die.
Dependencies are inferred from the claim text.