Method and apparatus for stress testing integrated circuits using an adjustable AC hot carrier injection source
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChien-Jung Wang, Shih-Liang Wang, Chao-Hao Cheng
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Abstract
A method and apparatus is provided for stress testing integrated circuits to determine their susceptibility to hot carrier charge injection damage. The system includes a hot carrier injection source formed on a semiconductor wafer carrying the ICs under test. The carrier source comprises an adjustable, voltage controlled oscillator having a variable frequency AC output test signal, and a modulator circuit for varying the duty cycle of the test signal applied to the ICs.
Claims13
An on-wafer hot carrier test system for stress testing integrated circuits formed on said wafer, comprising:
- an adjustable oscillator circuit for producing an alternating current test signal having a variable frequency, said oscillator circuit having an input and having an output coupled with each of said integrated circuits;
- and,
- a modulator circuit coupled with said oscillator circuit for adjusting the duty cycle of said test signal, wherein said modulator circuit includes a first input coupled with an adjustable voltage source, and the length of said duty cycle is related to the magnitude of the a signal delivered to said first input from said voltage source, said modulator circuit includes at least one transistor controlled by a bias voltage determined by the magnitude of the signal delivered to said first input from said voltage source.
A hot carrier test system formed on a semiconductor wafer for stress testing individual integrated circuits on said wafer, comprising:
- a variable frequency oscillator having an output for applying a test signal to an integrated circuit under test, said test signal having a changeable frequency, wherein said variable frequency oscillator includes an input for receiving a changeable voltage, the value of said voltage determining the frequency of said test signal;
- and,
- means coupled with said oscillator for adjusting a duty cycle of said test signal applied to said integrated circuit under test, wherein said duty cycle adjusting means includes a modulator circuit having an input connected with said oscillator output, and having an output, said modulator circuit includes a pair of transistors having their source-to-drain paths coupled in series, and controlled by the voltage of said test signal output by said oscillator.
A method for stress testing integrated circuits formed on a semiconductor wafer using hot carrier injection, comprising the steps of:
- (A) producing an A.C. test signal using an oscillator formed on said wafer;
- (B) adjusting the frequency of said test signal, by changing the value of a supply voltage, and applying said voltage to an input of said oscillator circuit;
- (C) adjusting the duty cycle of said test signal, by changing the value of a second supply voltage, and applying said second voltage to an input of said modulator circuit;
- and,
- (D) applying said test signal to an integrated circuit on said wafer.
Dependencies are inferred from the claim text.