G01R 31/318513
Test of multi-chip-moduls
Official title: {Test of Multi-Chip-Moduls}
G01R31/318513 (Test of multi-chip-moduls) appears on 338 US grants and 347 published applications in this corpus.
Search patents in G01R- Granted patents
- 338
- Published applications
- 347
- Assignees
- 128
- Inventors
- 576
- Latest grant
- 21 Jul 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1987 | 1 | 0 |
| 1988 | 0 | 0 |
| 1989 | 1 | 0 |
| 1990 | 0 | 0 |
| 1991 | 0 | 0 |
| 1992 | 1 | 0 |
| 1993 | 0 | 0 |
| 1994 | 2 | 0 |
| 1995 | 2 | 0 |
| 1996 | 3 | 0 |
| 1997 | 4 | 0 |
| 1998 | 2 | 0 |
| 1999 | 1 | 0 |
| 2000 | 1 | 0 |
| 2001 | 3 | 1 |
| 2002 | 3 | 1 |
| 2003 | 2 | 5 |
| 2004 | 9 | 8 |
| 2005 | 8 | 9 |
| 2006 | 6 | 10 |
| 2007 | 9 | 7 |
| 2008 | 5 | 15 |
| 2009 | 8 | 10 |
| 2010 | 8 | 7 |
| 2011 | 14 | 12 |
| 2012 | 7 | 12 |
| 2013 | 12 | 29 |
| 2014 | 19 | 24 |
| 2015 | 25 | 30 |
| 2016 | 27 | 25 |
| 2017 | 34 | 20 |
| 2018 | 16 | 14 |
| 2019 | 11 | 13 |
| 2020 | 16 | 14 |
| 2021 | 10 | 14 |
| 2022 | 16 | 12 |
| 2023 | 18 | 16 |
| 2024 | 18 | 11 |
| 2025 | 12 | 14 |
| 2026 | 4 | 14 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Wrapper cell design and built-in self-test architecture for 3DIC test and diagnosis21 Jul 2026US 12,687,578 B2Taiwan Semiconductor Manufacturing Company.Ltd
- System and method for schedule-based I/O multiplexing for integrated circuit (IC) scan test14 Jul 2026US 12,681,084 B1Marvell Asia Pte Ltd
- Testing circuitry in a stacked semiconductor device using through silicon vias12 May 2026US RE50,887 E1Longitude Licensing Limited
- Component communications in system-in-package systems27 Jan 2026US 12,535,839 B2Octavo Systems LLC
- On-chip distribution of test data for multiple dies2 Dec 2025US 12,487,282 B2Advanced Micro Devices Products (China) Co., Ltd.
- Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Test and Diagnosis8 Oct 2026US 2026/0309778 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Method and system for testing three-dimensional semiconductor devices27 Aug 2026US 2026/0251710 A1Marvell Asia Pte Ltd
- Semiconductor device for performing test operation of through-silicon vias13 Aug 2026US 2026/0235677 A1Samsung Electronics Co., Ltd.
- Die-to-die bypass mode for chiplet initialization, configuration, and communication6 Aug 2026US 2026/0228147 A1Microsoft Technology Licensing, LLC
- Systems and methods for isolating faults in die-to-die interconnects16 Jul 2026US 2026/0202469 A1Microsoft Technology Licensing, LLC
Most cited
By later US patents
- Apparatus for non-conductively interconnecting integrated circuits using half capacitors233US 5,629,838 APolychip, Inc. · 1997
- Method and apparatus for non-conductively interconnecting integrated circuits118US 6,728,113 B1Polychip, Inc. · 2004
- Method and apparatus for non-conductively interconnecting integrated circuits62US 6,916,719 B12005
- Electrostatic discharge protection for modular equipment58US 8,923,012 B2Rockwell Automation Technologies, Inc. · 2014
- Skew compensation for a stacked die55US 9,003,221 B1Xilinx, Inc. · 2015