Semiconductor device for performing test operation of through-silicon vias

A semiconductor device comprising:

• a memory die stack comprising a plurality of memory dies and implemented as a high-bandwidth memory (HBM), wherein the plurality of memory dies are electrically connected through a plurality of through-silicon vias (TSVs);
• and
• a system die comprising a system element, a system (SOC) controller configured to control the system element, and an HBM controller configured to control the plurality of memory dies in accordance with an operation of the system element,
• wherein the system die comprises a boundary scan chain and a plurality of TSV input/output (IO) cells configured to test a connectivity of the plurality of TSVs,
• wherein a TSV IO cell of the plurality of TSV IO cells comprises:
• a first port connected to a corresponding TSV of the plurality of TSVs;
• a second port connected to the boundary scan chain;
• a third port connected to the SOC controller;
• and
• a fourth port connected to the HBM controller, and
• wherein the SOC controller is configured to, in a test mode, provide test input data to the HBM controller and couple the first port of the TSV IO cell to the second port of the TSV IO cell, and in a normal mode, couple the third port the TSV IO cell to the first port of the TSV IO cell.

A method of testing a connectivity of a plurality of through-silicon vias (TSVs) of a memory die stack connected to a system die of a semiconductor device, the method comprising:

• receiving, from a system (SOC) controller of the system die, an input/output (IO) mode signal for controlling an operation mode of TSV IO cells, wherein a TSV IO cell of the plurality of TSV IO cells comprises a first port connected to a corresponding TSV of the plurality of TSVs, a second port connected to a boundary scan chain, and a third port connected to the SOC controller;
• providing, by the TSV IO cell, data of the controller received by the third port to the corresponding TSV connected to the first port based on a first logic level of the IO mode signal;
• providing, by the TSV IO cell, data of the corresponding TSV connected to the first port to the third port based on a second logic level of the IO mode signal;
• receiving, by the TSV IO cell, a boundary scan mode signal from the SOC controller;
• coupling, by the SOC controller in a test mode, the first port to the second port based on the boundary scan mode signal;
• receiving, by the boundary scan chain, a scan enable signal and a scan clock signal from the SOC controller;
• latching, by the boundary scan chain comprising a plurality of scan circuits respectively connected to the plurality of TSV IO cells, data of the corresponding TSV provided by the first port and provided to the second port of a corresponding TSV IO cell of the plurality of TSV IO cells based on the scan enable signal;
• and
• sequentially outputting, by the boundary scan chain, data latched to the plurality of scan circuits based on the scan clock signal.