H10W 90/26
The stacked chips being of the same size without any chips being
Official title: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
H10W90/26 (The stacked chips being of the same size without any chips being) appears on 1,946 US grants and 2,962 published applications in this corpus.
Search patents in H10W- Granted patents
- 1,946
- Published applications
- 2,962
- Assignees
- 319
- Inventors
- 3,771
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1988 | 3 | 0 |
| 1989 | 2 | 0 |
| 1990 | 0 | 0 |
| 1991 | 0 | 0 |
| 1992 | 1 | 0 |
| 1993 | 0 | 0 |
| 1994 | 1 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 0 | 0 |
| 1998 | 0 | 0 |
| 1999 | 0 | 0 |
| 2000 | 0 | 0 |
| 2001 | 1 | 1 |
| 2002 | 2 | 1 |
| 2003 | 3 | 9 |
| 2004 | 6 | 20 |
| 2005 | 9 | 13 |
| 2006 | 10 | 16 |
| 2007 | 7 | 8 |
| 2008 | 6 | 17 |
| 2009 | 6 | 14 |
| 2010 | 15 | 14 |
| 2011 | 16 | 48 |
| 2012 | 19 | 132 |
| 2013 | 83 | 143 |
| 2014 | 126 | 147 |
| 2015 | 144 | 157 |
| 2016 | 123 | 102 |
| 2017 | 108 | 106 |
| 2018 | 106 | 102 |
| 2019 | 103 | 139 |
| 2020 | 108 | 156 |
| 2021 | 141 | 208 |
| 2022 | 153 | 211 |
| 2023 | 188 | 293 |
| 2024 | 166 | 258 |
| 2025 | 187 | 236 |
| 2026 | 103 | 411 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Semiconductor package and method of manufacturing the same6 Oct 2026US 12,757,790 B2Samsung Electronics Co., Ltd.
- Direct bonding methods and structures29 Sep 2026US 12,751,323 B2Adeia Semiconductor Bonding Technologies Inc.
- Direct hybrid bond pad having tapered sidewall29 Sep 2026US 12,751,328 B2Adeia Semiconductor Bonding Technologies Inc.
- Semiconductor package22 Sep 2026US 12,745,678 B2Samsung Electronics Co., Ltd.
- Memory tile with probe pad arrangement and stacked memory device1 Sep 2026US 12,727,497 B2Powerchip Semiconductor Manufacturing Corporation
- Semiconductor devices including global bitlines8 Oct 2026US 2026/0313881 A1Samsung Electronics Co., Ltd.
- Semiconductor device with through electrode through mold structure8 Oct 2026US 2026/0313894 A1Samsung Electronics Co., Ltd.
- Semiconductor device including charge shielding layer8 Oct 2026US 2026/0314426 A1Samsung Electronics Co., Ltd.
- Semiconductor device with reduced warpage8 Oct 2026US 2026/0314478 A1Samsung Electronics Co., Ltd.
- Semiconductor package8 Oct 2026US 2026/0314497 A1Samsung Electronics Co., Ltd.
Most cited
By later US patents
- Method and apparatus for generating a device ID for stacked devices631US 7,111,149 B2Intel Corporation · 2006
- Method of stacking semiconductor substrates for fabrication of three-dimensional integrated circuit476US 5,087,585 ANEC Corporation · 1992
- Electronic packaging including die with through silicon via354US 7,317,256 B2Intel Corporation · 2008
- Integrated circuit with interface tile for coupling to a stacked-die second integrated circuit303US 7,068,072 B2Xilinx, Inc. · 2006
- Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same275US 8,802,495 B2Samsung Electronics Co., Ltd. · 2014