Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same

A method of manufacturing a semiconductor package comprising:

• preparing a parent substrate including a plurality of package board parts laterally spaced apart from each other;
• mounting first chips on the package board parts;
• forming a first mold layer on the parent substrate having the first chips;
• planarizing the first mold layer to expose the first chips;
• forming via-holes in the exposed first chips;
• forming through-via electrodes in the via-holes;
• mounting second chips on the first chips having the through-via electrodes;
• and
• forming a second mold layer on the parent substrate including the first chips and the second chips.

A method of manufacturing a semiconductor package comprising:

• providing first chips on a parent substrate, the first chips electrically coupled to the parent substrate, and each of the first chips including at least one first through-via electrode, a first end of each first through-via electrode electrically coupled to the parent substrate and a second end of each first through-via electrode inside a respective one of the first chips;
• providing a first mold layer on the first chips;
• planarizing the first mold layer to expose top surfaces of the first chips;
• thinning the first chips by etching the exposed top surfaces of the first chips such that the second ends of the first through-via electrodes are exposed;
• selectively providing a passivation layer on the etched top surfaces of the first chips such that the second ends of the first through-via electrodes are exposed;
• providing second chips on the first chips, each of the second chips electrically coupled to a corresponding one of the first chips;
• providing a second mold layer on the second chips;
• and
• singulating the resultant structure to form the semiconductor package.