Memory tile with probe pad arrangement and stacked memory device

A stacked memory device, comprising:

• a memory chip, having a plurality of memory tiles;
• a logic chip, bonded to the memory chip in a face-to-face manner and configured to control the memory chip,
• wherein each of the plurality of memory tiles further comprises:
• a first surface and a second surface opposite to the first surface;
• a first probe pad set, having a plurality of first probe pads and provided on the first surface;
• a second probe pad set, having a plurality of second probe pads and provided on the second surface;
• a plurality of first conductive connections, each of the plurality of first conductive connections is electrically connected to a corresponding first probe pad among the first probe pad set;
• a plurality of second conductive connections, each of the plurality of second conductive connections is electrically connected to a corresponding first conductive connection among the plurality of first conductive connections;
• a plurality of third conductive connections, each of the plurality of third conductive connections is electrically connected to a corresponding second conductive connection among the plurality of second conductive connections;
• and
• a plurality of fourth conductive connections, each of the plurality of fourth conductive connections is electrically connected to a corresponding third conductive connection among the plurality of third conductive connections and is electrically connected to a corresponding second probe pad among the second probe pad set,
• wherein a first arrangement pattern of the first probe pad set is the same as a second arrangement pattern of the second probe pad set,
• the plurality of first probe pads of the first probe pad set each receives a corresponding first test signal to form a first test signal arrangement pattern, and the plurality of second probe pads of the second probe pad set each receives a corresponding second test signal to form a second test signal arrangement pattern, wherein the first test signal arrangement pattern received by the first probe pad set has two rows symmetrically lined up with respect to a first central line, and the second test signal arrangement pattern received by the second probe pad set has two rows symmetrically lined up with respect to a second central line, and
• the first test signal arrangement pattern on the first surface is the same as the second test signal arrangement pattern on the second surface, such that a same probe card is applied to the first probe pad set and the second probe pad set to test the first surface or the second surface of the memory tile.

A memory tile with a probe pad arrangement, comprising:

• a first surface and a second surface opposite to the first surface;
• a first probe pad set, having a plurality of first probe pads and provided on the first surface;
• a second probe pad set, having a plurality of second probe pads and provided on the second surface;
• and
• a plurality of connection structures, each of the plurality of connection structures being electrically connected to a corresponding first probe pad among the plurality of first probe pads and to a corresponding second probe pad among the plurality of second probe pads,
• wherein a first arrangement pattern of the first probe pad set is the same as a second arrangement pattern of the second probe pad set,
• the plurality of first probe pads of the first probe pad set each receives a corresponding first test signal to form a first test signal arrangement pattern, and the plurality of second probe pads of the second probe pad set each receives a corresponding second test signal to form a second test signal arrangement pattern, wherein the first test signal arrangement pattern received by the first probe pad set has two rows symmetrically lined up with respect to a first central line, and the second test signal arrangement pattern received by the second probe pad set has two rows symmetrically lined up with respect to a second central line, and
• the first test signal arrangement pattern on the first surface is the same as the second test signal arrangement pattern on the second surface, such that a same probe card is applied to the first probe pad set and the second probe pad set to test the first surface or the second surface of the memory tile.