US 12,745,678 B2Granted

Semiconductor package

AssigneeSamsung Electronics Co., Ltd.

InventorsMinseung Ji, Seungduk Baek, Aenee Jang

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Abstract

A semiconductor package includes a lower chip including a first lower bonding pad and a second lower bonding pad, and an upper chip disposed on the lower chip, the upper chip including a first upper bonding pad and a second upper bonding pad respectively hybrid-bonded together. The first lower and upper bonding pads have a first shape in which first and second axis lengths are the same, and are disposed in a first center region of the chips. The second lower and upper bonding pads have a second shape in which third and fourth axis lengths differ, and are disposed in a first edge region which is near a corner point of the chip. In the second lower and upper bonding pads disposed in the first edge region, the third axis length is arranged in a direction perpendicular to a radial direction from the center point.

Claims20

Dependent claims

A semiconductor package comprising:

a lower chip including a lower bonding insulation layer, a first lower bonding pad, and a second lower bonding pad;
and
an upper chip disposed on the lower chip, the upper chip including an upper bonding insulation layer, a first upper bonding pad, and a second upper bonding pad respectively hybrid-bonded to the lower bonding insulation layer, the first lower bonding pad, and the second lower bonding pad,
wherein each of the first lower bonding pad and the first upper bonding pad have a first shape in which a first axis length is the same as a second axis length, and the first lower bonding pad and the first upper bonding pad are disposed one-dimensionally or planarily in a first center region which is near a center point of the lower chip and the upper chip,
each of the second lower bonding pad and the second upper bonding pad have a second shape in which a third axis length differs from a fourth axis length, and the second lower bonding pad and the second upper bonding pad are disposed one-dimensionally or planarily in a first edge region which is near a corner point of the lower chip and the upper chip, and the third axis length is greater than the first axis length, and
in the second lower bonding pad and the second upper bonding pad disposed in the first edge region, the third axis length is arranged in a direction perpendicular to a radial direction from the center point.

3 more elements

A semiconductor package comprising:

a lower chip including a lower bonding insulation layer, a first lower bonding pad, and a second lower bonding pad;
and
an upper chip disposed on the lower chip, the upper chip including an upper bonding insulation layer, a first upper bonding pad, and a second upper bonding pad respectively hybrid-bonded to the lower bonding insulation layer, the first lower bonding pad, and the second lower bonding pad,
wherein the first lower bonding pad and the first upper bonding pad each have a circular shape and are one-dimensionally or planarily arranged in a first center region that is disposed near a center point of the lower chip and the upper chip,
the second lower bonding pad and the second upper bonding pad each having an oval shape are one-dimensionally or planarily arranged in a perpendicular direction, which is perpendicular to a radial direction from the center point, the second lower bonding pad and the second upper bonding pad being disposed in a first edge region that is disposed near corner points of the lower chip and the upper chip, and a long-axis length of the oval shape is greater than a diameter of the circular shape, and
the second lower bonding pad and the second upper bonding pad of the first edge region are arranged to be one-dimensionally or planarily staggered, and partially staggered in the perpendicular direction perpendicular to the radial direction from the center point.

3 more elements

A semiconductor package comprising:

a lower chip including a lower bonding insulation layer, a first lower bonding pad, and a second lower bonding pad;
and
an upper chip disposed on the lower chip, the upper chip including an upper bonding insulation layer, a first upper bonding pad, and a second upper bonding pad respectively hybrid-bonded to the lower bonding insulation layer, the first lower bonding pad, and the second lower bonding pad,
wherein the first lower bonding pad and the first upper bonding pad each having a tetragonal shape are one-dimensionally or planarily arranged in a first center region that is disposed near a center point of the lower chip and the upper chip,
the second lower bonding pad and the second upper bonding pad each having a rectangular shape are one-dimensionally or planarily arranged in a perpendicular direction, which is perpendicular to a radial direction from the center point, the second lower bonding pad and the second upper bonding pad being disposed in a first edge region that is disposed near corner points of the lower chip and the upper chip, and a long-axis length of the rectangular shape is greater than an axis length of the tetragonal shape, and
the second lower bonding pad and the second upper bonding pad of the first edge region are arranged to be one-dimensionally or planarily staggered, and partially staggered in the perpendicular direction perpendicular to the radial direction from the center point.

3 more elements

Dependencies are inferred from the claim text.