H10W 72/952
Comprising metals or metalloids
Official title: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
H10W72/952 (Comprising metals or metalloids) appears on 15,470 US grants and 17,270 published applications in this corpus.
Search patents in H10W- Granted patents
- 15,470
- Published applications
- 17,270
- Assignees
- 1,895
- Inventors
- 20,198
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 6 | 0 |
| 1977 | 16 | 0 |
| 1978 | 9 | 0 |
| 1979 | 8 | 0 |
| 1980 | 9 | 0 |
| 1981 | 7 | 0 |
| 1982 | 6 | 0 |
| 1983 | 6 | 0 |
| 1984 | 8 | 0 |
| 1985 | 11 | 0 |
| 1986 | 11 | 0 |
| 1987 | 19 | 0 |
| 1988 | 19 | 0 |
| 1989 | 30 | 0 |
| 1990 | 38 | 0 |
| 1991 | 56 | 0 |
| 1992 | 53 | 0 |
| 1993 | 45 | 0 |
| 1994 | 58 | 0 |
| 1995 | 63 | 0 |
| 1996 | 76 | 0 |
| 1997 | 90 | 0 |
| 1998 | 139 | 0 |
| 1999 | 179 | 0 |
| 2000 | 218 | 0 |
| 2001 | 279 | 132 |
| 2002 | 325 | 382 |
| 2003 | 326 | 383 |
| 2004 | 330 | 433 |
| 2005 | 334 | 607 |
| 2006 | 359 | 618 |
| 2007 | 386 | 681 |
| 2008 | 373 | 723 |
| 2009 | 384 | 574 |
| 2010 | 521 | 687 |
| 2011 | 548 | 625 |
| 2012 | 572 | 682 |
| 2013 | 633 | 691 |
| 2014 | 667 | 720 |
| 2015 | 703 | 850 |
| 2016 | 775 | 765 |
| 2017 | 818 | 805 |
| 2018 | 687 | 674 |
| 2019 | 676 | 825 |
| 2020 | 750 | 1018 |
| 2021 | 760 | 1045 |
| 2022 | 777 | 906 |
| 2023 | 744 | 706 |
| 2024 | 685 | 761 |
| 2025 | 544 | 622 |
| 2026 | 334 | 355 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Bondable pillars for wire bonds in a semiconductor package6 Oct 2026US 12,757,414 B2Micron Technology, Inc.
- Semiconductor package and manufacturing method thereof6 Oct 2026US 12,757,764 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Wafer-level hybrid bonded RF switch with redistribution layer6 Oct 2026US 12,757,792 B2Qorvo US, Inc.
- Semiconductor package and method of manufacturing the same6 Oct 2026US 12,757,796 B2Samsung Electronics Co., Ltd.
- Multiple plated via arrays of different wire heights on a same substrate6 Oct 2026US RE51,062 E1Adeia Semiconductor Technologies LLC
- Integrated chips package structure with capacitor8 Oct 2026US 2026/0313919 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor packages and methods of manufacturing thereof8 Oct 2026US 2026/0314284 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Package structure and method for fabricating the same8 Oct 2026US 2026/0314354 A1National Yang Ming.Chiao Tung University
- Semiconductor structures with through via8 Oct 2026US 2026/0314366 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Layer-by-layer formation of through-substrate via8 Oct 2026US 2026/0314369 A1Taiwan Semiconductor Manufacturing Company.Ltd
Most cited
By later US patents
- Testing of semiconductor chips with microbumps1,870US 9,372,206 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2016
- Methods and apparatus of wafer level package for heterogeneous integration technology1,051US 9,111,949 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2015
- Fan-out interconnect structure and method for forming same1,030US 9,368,460 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2016
- 3DIC stacking device and method of manufacture962US 9,443,783 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2016
- Methods and devices for fabricating and assembling printable semiconductor elements883US 7,622,367 B1The Board of Trustees of the University of Illinois · 2009