Wafer-level hybrid bonded RF switch with redistribution layer

An integrated circuit (IC) device, comprising:

• a buried oxide layer;
• a trap rich layer;
• a handle layer;
• a first active semiconductor layer that includes first active semiconductor device regions, wherein the first active semiconductor layer is positioned on the buried oxide layer, the trap rich layer is positioned on the buried box layer, and the handle layer is positioned on the trap rich layer;
• a second active semiconductor layer that includes active semiconductor regions, the second active semiconductor layer being connected to the first active semiconductor layer and being positioned over the first active semiconductor layer;
• a first back end of line (BEOL) having a first conductive structure that is electrically connected to the first active semiconductor layer;
• a second BEOL having a second conductive structure that is electrically connected to the second active semiconductor layer;
• a hybrid bonding layer with a third conductive structure that electrically connects the first conductive structure to the second conductive structure, wherein:
• the first BEOL is positioned under the hybrid bonding layer;
• the first BEOL is positioned on the first active semiconductor layer;
• the hybrid bonding layer is positioned between the first BEOL and the second BEOL;
• the second BEOL is positioned between the hybrid bonding layer and the second active semiconductor layer;
• a first redistribution layer positioned over the second active semiconductor layer, the first redistribution layer is electrically connected to the first active semiconductor layer and the second active semiconductor layer;
• a passivation layer positioned on the first redistribution layer;
• a second redistribution layer positioned over the passivation layer, wherein the second redistribution layer is electrically connected to the first redistribution layer.

A method of manufacturing an integrated circuit (IC), comprising:

• providing an IC device that comprises:
• a buried oxide layer;
• a trap rich layer;
• a handle layer;
• a first active semiconductor layer that includes a first active semiconductor device regions, wherein the first active semiconductor layer is positioned on the buried oxide layer, the trap rich layer is positioned on the buried box layer, and the handle layer is positioned on the trap rich layer;
• a first back end of line (BEOL) positioned on the first active semiconductor layer;
• a first conductive structure is integrated into the first BEOL and connects to at least one of the first active semiconductor device regions;
• a second active semiconductor layer that includes second active semiconductor device regions;
• a second BEOL positioned on the second active semiconductor layer, wherein a second conductive structure is integrated into the second BEOL and connects to at least one of the second active semiconductor regions, wherein the second conductive structure is electrically connected to the first conductive structure;
• and
• a hybrid bonding layer with a third conductive structure integrated into the hybrid bonding layer, wherein:
• the first BEOL is positioned under the hybrid bonding layer;
• the second BEOL is positioned on the hybrid bonding layer;
• and
• the third conductive structure electrically connects the first conductive structure to the second conductive structure;
• forming a first redistribution layer positioned over the second active semiconductor layer, the first redistribution layer is electrically connected to the second conductive structure;
• forming a passivation layer positioned on the first redistribution layer;
• forming a second redistribution layer positioned over the passivation layer, wherein the second redistribution layer is electrically connected to the first redistribution layer.