H10W 72/01925
In solid form
Official title: {in solid form}
H10W72/01925 (In solid form) appears on 117 US grants and 141 published applications in this corpus.
Search patents in H10W- Granted patents
- 117
- Published applications
- 141
- Assignees
- 64
- Inventors
- 270
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1991 | 1 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 0 | 0 |
| 1998 | 0 | 0 |
| 1999 | 1 | 0 |
| 2000 | 0 | 0 |
| 2001 | 2 | 1 |
| 2002 | 0 | 4 |
| 2003 | 2 | 2 |
| 2004 | 3 | 2 |
| 2005 | 3 | 0 |
| 2006 | 0 | 0 |
| 2007 | 0 | 2 |
| 2008 | 0 | 3 |
| 2009 | 1 | 2 |
| 2010 | 3 | 4 |
| 2011 | 2 | 4 |
| 2012 | 2 | 7 |
| 2013 | 7 | 9 |
| 2014 | 9 | 10 |
| 2015 | 5 | 13 |
| 2016 | 10 | 12 |
| 2017 | 14 | 14 |
| 2018 | 11 | 7 |
| 2019 | 8 | 8 |
| 2020 | 7 | 9 |
| 2021 | 4 | 6 |
| 2022 | 3 | 4 |
| 2023 | 9 | 5 |
| 2024 | 2 | 7 |
| 2025 | 5 | 4 |
| 2026 | 3 | 2 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Multiple plated via arrays of different wire heights on a same substrate6 Oct 2026US RE51,062 E1Adeia Semiconductor Technologies LLC
- Through-substrate conductor support11 Aug 2026US 12,703,625 B2Texas Instruments Incorporated
- Semiconductor die package14 Apr 2026US 12,604,752 B2Infineon Technologies Austria AG
- Conductive buffer layers for semiconductor die assemblies and associated systems and methods27 May 2025US 12,315,833 B2Micron Technology, Inc.
- Heterogeneous nested interposer package for IC chips8 Apr 2025US 12,272,656 B2Intel Corporation
- Semiconductor Device and Method of Fabricating the Same4 Jun 2026US 2026/0157166 A1United Microelectronics Corp.
- Method of joining electrical and mechanical components using laminated modular preforms30 Apr 2026US 2026/0123502 A1Alpha Assembly Solutions Inc.
- Conductive buffer layers for semiconductor die assemblies and associated systems and methods4 Sep 2025US 2025/0279379 A1Micron Technology, Inc.
- Heterogeneous nested interposer package for ic chips19 Jun 2025US 2025/0201734 A1Intel Corporation
- Sinter ready multilayer wire/ribbon bond pads and method for die top attachment19 Jun 2025US 2025/0201741 A1
Most cited
By later US patents
- Semiconductor components having encapsulated through wire interconnects (TWI)62US 7,659,612 B2Micron Technology, Inc. · 2010
- Multiple bond via arrays of different wire heights on a same substrate61US 9,263,394 B2Invensas Corporation · 2016
- Multiple bond via arrays of different wire heights on a same substrate49US 9,583,456 B2Invensas Corporation · 2017
- Interconnections for a semiconductor device and method for forming same45US 6,709,893 B2Micron Technology, Inc. · 2004
- Fan-out wafer level package with polymeric layer for high reliability37US 8,436,255 B2Stmicroelectronics Pte Ltd · 2013