Heterogeneous nested interposer package for ic chips

An electronics package, comprising:

• an interposer comprising silicon, the interposer comprising vias that provide connections between pads on a bottom of the interposer and a redistribution layer on a top of the interposer, the interposer having a cavity therein;
• a component in the cavity of the interposer;
• a first die over the interposer, the first die coupled to the redistribution layer of the interposer by first interconnects, and the first die coupled to the component by second interconnects;
• a second die over the interposer and laterally spaced apart from the first die, the second die coupled to the redistribution layer of the interposer by third interconnects, and the second die coupled to the component by fourth interconnects;
• and
• a mold layer between the first die and the interposer and between the second die and the interposer, the mold layer laterally between and in contact with the first die and the second die, and the mold layer in contact with the first interconnects, the second interconnects, the third interconnects and the fourth interconnects.