Heterogeneous nested interposer package for IC chips
AssigneeIntel Corporation
InventorsDebendra Mallik, Ravindranath Mahajan, Robert Sankman, Shawna Liff, Srinivas Pietambaram, Bharat Penmecha
Life of this patent
Estimating the term…
Abstract
Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.
Claims20
An electronics package, comprising:
- a first mold layer;
- a bridge embedded in the first mold layer, the bridge comprising through component vias;
- a passive component embedded in the first mold layer, the passive component laterally spaced apart from the bridge;
- a first die over a first portion of the bridge;
- a second die over a second portion of the bridge and over the passive component, the second die laterally spaced apart from the first die, wherein the bridge electrically couples the first die and the second die, and wherein the second die is electrically coupled to the passive component;
- a redistribution layer between the bridge and the first die and between the bridge and the second die;
- and
- a second mold layer laterally between the first die and the second die.
An electronics package, comprising:
- an underfill material layer;
- a first nested component embedded in the underfill material layer, the first nested component comprising through component vias;
- a second nested component embedded in the underfill material layer, the second nested component laterally spaced apart from the first nested component;
- a first die over a first portion of the first nested component;
- a second die over a second portion of the first nested component and over the second nested component, the second die laterally spaced apart from the first die, wherein the first nested component electrically couples the first die and the second die, and wherein the second die is electrically coupled to the second nested component;
- a redistribution layer between the first nested component and the first die and between the first nested component and the second die;
- and
- a mold layer laterally between the first die and the second die.
A method of fabricating an electronics package, the method comprising:
- embedding a bridge embedded in a first mold layer, the bridge comprising through component vias;
- embedding a passive component in the first mold layer, the passive component laterally spaced apart from the bridge;
- providing a first die over a first portion of the bridge;
- providing a second die over a second portion of the bridge and over the passive component, the second die laterally spaced apart from the first die, wherein the bridge electrically couples the first die and the second die, and wherein the second die is electrically coupled to the passive component;
- forming a redistribution layer between the bridge and the first die and between the bridge and the second die;
- and
- forming a second mold layer laterally between the first die and the second die.
Dependencies are inferred from the claim text.