H10W 72/01255
By using masks
Official title: {by using masks}
H10W72/01255 (By using masks) appears on 2,734 US grants and 3,046 published applications in this corpus.
Search patents in H10W- Granted patents
- 2,734
- Published applications
- 3,046
- Assignees
- 548
- Inventors
- 4,030
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 1 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 1 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 1 | 0 |
| 1987 | 0 | 0 |
| 1988 | 2 | 0 |
| 1989 | 3 | 0 |
| 1990 | 7 | 0 |
| 1991 | 5 | 0 |
| 1992 | 12 | 0 |
| 1993 | 14 | 0 |
| 1994 | 13 | 0 |
| 1995 | 15 | 0 |
| 1996 | 25 | 0 |
| 1997 | 10 | 0 |
| 1998 | 22 | 0 |
| 1999 | 28 | 0 |
| 2000 | 41 | 0 |
| 2001 | 55 | 30 |
| 2002 | 68 | 73 |
| 2003 | 80 | 104 |
| 2004 | 87 | 121 |
| 2005 | 77 | 125 |
| 2006 | 67 | 130 |
| 2007 | 66 | 203 |
| 2008 | 92 | 169 |
| 2009 | 78 | 112 |
| 2010 | 100 | 95 |
| 2011 | 119 | 133 |
| 2012 | 116 | 130 |
| 2013 | 124 | 168 |
| 2014 | 132 | 163 |
| 2015 | 150 | 166 |
| 2016 | 156 | 122 |
| 2017 | 142 | 141 |
| 2018 | 125 | 109 |
| 2019 | 99 | 128 |
| 2020 | 124 | 142 |
| 2021 | 121 | 139 |
| 2022 | 101 | 115 |
| 2023 | 76 | 68 |
| 2024 | 94 | 61 |
| 2025 | 63 | 51 |
| 2026 | 22 | 48 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Multiple plated via arrays of different wire heights on a same substrate6 Oct 2026US RE51,062 E1Adeia Semiconductor Technologies LLC
- Semiconductor device with a metal array portion with removed corners to reduce metal portion height variations15 Sep 2026US 12,740,466 B2Kabushiki Kaisha Toshiba
- Sintered metal flip chip joints18 Aug 2026US 12,713,938 B2Texas Instruments Incorporated
- Method of making semiconductor device having reduced bump height variation28 Jul 2026US 12,696,784 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Three-dimensional stacking semiconductor assemblies with near zero bond line thickness14 Jul 2026US 12,685,233 B2Micron Technology, Inc.
- Semiconductor packages with separately plated metal pillars1 Oct 2026US 2026/0305410 A1Texas Instruments Incorporated
- Method for manufacturing semiconductor device1 Oct 2026US 2026/0305435 A1Resonac Corporation
- Semiconductor structure and fabrication method thereof1 Oct 2026US 2026/0305439 A1United Microelectronics Corp.
- Combined via and solder bump for three-dimensional integration of an infrared detector3 Sep 2026US 2026/0262527 A1Semiconductor Components Industries, LLC
- Semiconductor structure and manufacturing method threreof3 Sep 2026US 2026/0262528 A1Siliconware Precision Industries Co., Ltd.
Most cited
By later US patents
- Testing of semiconductor chips with microbumps1,870US 9,372,206 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2016
- Process of fabricating three-dimensional semiconductor device576US 4,612,083 ANEC Corporation · 1986
- Semiconductor integrated circuit device and method of manufacturing the same437US 4,982,265 AAkita Electronics Co., Ltd. · 1991
- Multi-chip programmable logic device having configurable logic circuitry and configuration data storage on different dice399US 6,917,219 B2Xilinx, Inc. · 2005
- Pillar connections for semiconductor chips and method of manufacture392US 6,578,754 B1Advanpack Solutions Pte Ltd. · 2003