Three-dimensional stacking semiconductor assemblies with near zero bond line thickness
AssigneeMicron Technology, Inc.
InventorOwen R. Fay
Life of this patent
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Abstract
Semiconductor device package assemblies and associated methods are disclosed herein. In some embodiments, the semiconductor device package assembly includes (1) a base component having a front side and a back side opposite the first side, the base component having a first metallization structure at the front side, the first metallization structure being exposed in a contacting area at the front side; (2) a semiconductor device package having a first side and a second side, the semiconductor device package having a second metallization structure at the first side; and (3) a metal bump at least partially positioned in the recess and electrically coupled to the second metallization structure and the first metallization structure.
Claims18
A semiconductor device, comprising:
- a semiconductor substrate including a front side and a back side opposite the front side;
- a metallization structure at the front side of the semiconductor substrate, the metallization structure including first, second, and third metallization layers, the metallization structure being exposed from the back side of the semiconductor substrate via a cavity extending through the semiconductor substrate;
- and
- a metal pillar at least partially positioned in the cavity and electrically coupled to the metallization structure, the metal pillar extending from the third metallization layer past the back side of the semiconductor substrate.
A semiconductor device, comprising:
- a semiconductor substrate including a front side and a back side opposite the front side;
- a metallization structure at the front side of the semiconductor substrate, the metallization structure including first, second, and third metallization layers, the metallization structure being exposed from the back side of the semiconductor substrate via a cavity extending through the semiconductor substrate;
- a metal bump at least partially positioned in the cavity and electrically coupled to the metallization structure, the metal bump extending from the third metallization layer past the back side of the semiconductor substrate.
A semiconductor device, comprising:
- a semiconductor substrate including a front side and a back side opposite the front side;
- a metallization structure at the front side of the semiconductor substrate, the metallization structure including first, second, and third metallization layers, the metallization structure being exposed from the back side via a cavity extending through the semiconductor substrate;
- a metal bump or pillar at positioned on the metallization structure and extending away from the cavity, the metal bump or pillar having a height greater than a depth of the cavity.
Dependencies are inferred from the claim text.